Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T7
0	1	Covered	T7,T36,T37
1	0	Covered	T10,T11,T12

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T7,T33
1	0	Covered	T12,T56,T30
1	1	Covered	T10,T11,T12

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	155494041	7192	0	0
GateOpen_A	155494041	13752	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155494041	7192	0	0
T7	578814	75	0	0
T8	137979	0	0	0
T11	6589	4	0	0
T12	7585	17	0	0
T30	0	1	0	0
T32	13055	0	0	0
T33	6606	3	0	0
T34	4683	0	0	0
T35	6626	0	0	0
T36	9381	21	0	0
T37	0	67	0	0
T38	46110	0	0	0
T41	0	4	0	0
T43	0	11	0	0
T50	0	1	0	0
T56	0	13	0	0
T126	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155494041	13752	0	0
T7	578814	91	0	0
T8	137979	0	0	0
T9	0	1	0	0
T10	20679	4	0	0
T11	6589	4	0	0
T12	7585	21	0	0
T32	13055	4	0	0
T33	6606	3	0	0
T34	4683	0	0	0
T35	6626	4	0	0
T36	9381	25	0	0
T38	0	4	0	0
T49	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T7
0	1	Covered	T7,T36,T37
1	0	Covered	T10,T11,T12

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T7,T36
1	0	Covered	T12,T56,T30
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	16729405	1719	0	0
GateOpen_A	16729405	3357	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729405	1719	0	0
T7	62380	17	0	0
T8	14996	0	0	0
T11	724	1	0	0
T12	821	4	0	0
T30	0	1	0	0
T32	1523	0	0	0
T33	728	0	0	0
T34	512	0	0	0
T35	723	0	0	0
T36	1036	6	0	0
T37	0	16	0	0
T38	5106	0	0	0
T41	0	1	0	0
T43	0	3	0	0
T56	0	3	0	0
T126	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729405	3357	0	0
T7	62380	21	0	0
T8	14996	0	0	0
T9	0	1	0	0
T10	3123	1	0	0
T11	724	1	0	0
T12	821	5	0	0
T32	1523	1	0	0
T33	728	0	0	0
T34	512	0	0	0
T35	723	1	0	0
T36	1036	7	0	0
T38	0	1	0	0
T49	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T7
0	1	Covered	T7,T36,T37
1	0	Covered	T10,T11,T12

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T7,T33
1	0	Covered	T12,T56,T30
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	33459182	1838	0	0
GateOpen_A	33459182	3476	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33459182	1838	0	0
T7	124766	19	0	0
T8	29991	0	0	0
T11	1447	1	0	0
T12	1641	4	0	0
T32	3046	0	0	0
T33	1455	1	0	0
T34	1027	0	0	0
T35	1446	0	0	0
T36	2072	5	0	0
T37	0	17	0	0
T38	10211	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T56	0	3	0	0
T126	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33459182	3476	0	0
T7	124766	23	0	0
T8	29991	0	0	0
T10	6246	1	0	0
T11	1447	1	0	0
T12	1641	5	0	0
T32	3046	1	0	0
T33	1455	1	0	0
T34	1027	0	0	0
T35	1446	1	0	0
T36	2072	6	0	0
T38	0	1	0	0
T49	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T7
0	1	Covered	T7,T36,T37
1	0	Covered	T10,T11,T12

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T7,T33
1	0	Covered	T12,T56,T30
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	68805145	1831	0	0
GateOpen_A	68805145	3473	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68805145	1831	0	0
T7	259188	20	0	0
T8	60074	0	0	0
T11	2945	1	0	0
T12	3403	4	0	0
T32	5657	0	0	0
T33	2949	1	0	0
T34	2096	0	0	0
T35	2971	0	0	0
T36	4182	4	0	0
T37	0	18	0	0
T38	20528	0	0	0
T41	0	1	0	0
T43	0	4	0	0
T50	0	1	0	0
T56	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68805145	3473	0	0
T7	259188	24	0	0
T8	60074	0	0	0
T10	7540	1	0	0
T11	2945	1	0	0
T12	3403	5	0	0
T32	5657	1	0	0
T33	2949	1	0	0
T34	2096	0	0	0
T35	2971	1	0	0
T36	4182	5	0	0
T38	0	1	0	0
T49	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T7
0	1	Covered	T7,T36,T37
1	0	Covered	T10,T11,T12

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T7,T33
1	0	Covered	T12,T56,T57
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	36500309	1804	0	0
GateOpen_A	36500309	3446	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36500309	1804	0	0
T7	132480	19	0	0
T8	32918	0	0	0
T11	1473	1	0	0
T12	1720	5	0	0
T32	2829	0	0	0
T33	1474	1	0	0
T34	1048	0	0	0
T35	1486	0	0	0
T36	2091	6	0	0
T37	0	16	0	0
T38	10265	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T56	0	4	0	0
T126	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36500309	3446	0	0
T7	132480	23	0	0
T8	32918	0	0	0
T10	3770	1	0	0
T11	1473	1	0	0
T12	1720	6	0	0
T32	2829	1	0	0
T33	1474	1	0	0
T34	1048	0	0	0
T35	1486	1	0	0
T36	2091	7	0	0
T38	0	1	0	0
T49	0	1	0	0