Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	163009940	26627	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163009940	26627	0	0
T1	845090	215	0	0
T2	0	285	0	0
T3	0	562	0	0
T16	0	113	0	0
T17	0	74	0	0
T18	0	143	0	0
T19	0	327	0	0
T20	0	318	0	0
T21	0	188	0	0
T22	0	371	0	0
T23	9310	0	0	0
T24	7745	0	0	0
T25	8070	0	0	0
T26	7580	0	0	0
T27	9210	0	0	0
T28	5755	0	0	0
T29	317895	0	0	0
T30	3520	0	0	0
T31	50825	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	32601988	3966	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	3966	0	0
T1	169018	32	0	0
T2	0	45	0	0
T3	0	83	0	0
T16	0	14	0	0
T17	0	11	0	0
T18	0	20	0	0
T19	0	53	0	0
T20	0	42	0	0
T21	0	30	0	0
T22	0	47	0	0
T23	1862	0	0	0
T24	1549	0	0	0
T25	1614	0	0	0
T26	1516	0	0	0
T27	1842	0	0	0
T28	1151	0	0	0
T29	63579	0	0	0
T30	704	0	0	0
T31	10165	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	32601988	3913	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	3913	0	0
T1	169018	27	0	0
T2	0	45	0	0
T3	0	82	0	0
T16	0	16	0	0
T17	0	11	0	0
T18	0	20	0	0
T19	0	52	0	0
T20	0	41	0	0
T21	0	29	0	0
T22	0	54	0	0
T23	1862	0	0	0
T24	1549	0	0	0
T25	1614	0	0	0
T26	1516	0	0	0
T27	1842	0	0	0
T28	1151	0	0	0
T29	63579	0	0	0
T30	704	0	0	0
T31	10165	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	32601988	5357	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	5357	0	0
T1	169018	41	0	0
T2	0	59	0	0
T3	0	112	0	0
T16	0	23	0	0
T17	0	15	0	0
T18	0	29	0	0
T19	0	68	0	0
T20	0	66	0	0
T21	0	38	0	0
T22	0	73	0	0
T23	1862	0	0	0
T24	1549	0	0	0
T25	1614	0	0	0
T26	1516	0	0	0
T27	1842	0	0	0
T28	1151	0	0	0
T29	63579	0	0	0
T30	704	0	0	0
T31	10165	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	32601988	5350	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	5350	0	0
T1	169018	43	0	0
T2	0	57	0	0
T3	0	112	0	0
T16	0	23	0	0
T17	0	15	0	0
T18	0	29	0	0
T19	0	66	0	0
T20	0	63	0	0
T21	0	38	0	0
T22	0	73	0	0
T23	1862	0	0	0
T24	1549	0	0	0
T25	1614	0	0	0
T26	1516	0	0	0
T27	1842	0	0	0
T28	1151	0	0	0
T29	63579	0	0	0
T30	704	0	0	0
T31	10165	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	32601988	8041	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	8041	0	0
T1	169018	72	0	0
T2	0	79	0	0
T3	0	173	0	0
T16	0	37	0	0
T17	0	22	0	0
T18	0	45	0	0
T19	0	88	0	0
T20	0	106	0	0
T21	0	53	0	0
T22	0	124	0	0
T23	1862	0	0	0
T24	1549	0	0	0
T25	1614	0	0	0
T26	1516	0	0	0
T27	1842	0	0	0
T28	1151	0	0	0
T29	63579	0	0	0
T30	704	0	0	0
T31	10165	0	0	0