Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T4,T37

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	32601988	29632326	0	0
AllClkBypReqTrue_A	32601988	77586	0	0
IoClkBypReqFalse_A	32601988	29578166	0	2415
IoClkBypReqTrue_A	32601988	127176	0	0
LcClkBypAckFalse_A	32601988	29637602	0	0
LcClkBypAckTrue_A	32601988	72310	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	29632326	0	0
T7	149997	136456	0	0
T8	16922	16879	0	0
T10	1570	1471	0	0
T11	1473	1405	0	0
T12	1049	1011	0	0
T32	1413	1347	0	0
T33	1505	1414	0	0
T34	2095	1777	0	0
T35	1546	1461	0	0
T36	915	888	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	77586	0	0
T7	149997	415	0	0
T8	16922	0	0	0
T10	1570	56	0	0
T11	1473	0	0	0
T12	1049	0	0	0
T32	1413	42	0	0
T33	1505	0	0	0
T34	2095	87	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	54	0	0
T39	0	31	0	0
T40	0	364	0	0
T84	0	267	0	0
T85	0	67	0	0
T86	0	56	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	29578166	0	2415
T7	149997	136041	0	3
T8	16922	16877	0	3
T10	1570	1351	0	3
T11	1473	1403	0	3
T12	1049	1009	0	3
T32	1413	1204	0	3
T33	1505	1412	0	3
T34	2095	1665	0	3
T35	1546	1459	0	3
T36	915	886	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	127176	0	0
T7	149997	818	0	0
T8	16922	0	0	0
T10	1570	174	0	0
T11	1473	0	0	0
T12	1049	0	0	0
T32	1413	183	0	0
T33	1505	0	0	0
T34	2095	197	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	52	0	0
T39	0	62	0	0
T40	0	486	0	0
T49	0	61	0	0
T84	0	433	0	0
T85	0	21	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	29637602	0	0
T7	149997	136401	0	0
T8	16922	16879	0	0
T10	1570	1425	0	0
T11	1473	1405	0	0
T12	1049	1011	0	0
T32	1413	1274	0	0
T33	1505	1414	0	0
T34	2095	1826	0	0
T35	1546	1461	0	0
T36	915	888	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	72310	0	0
T7	149997	470	0	0
T8	16922	0	0	0
T10	1570	102	0	0
T11	1473	0	0	0
T12	1049	0	0	0
T32	1413	115	0	0
T33	1505	0	0	0
T34	2095	38	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	14	0	0
T39	0	18	0	0
T40	0	244	0	0
T84	0	302	0	0
T85	0	18	0	0
T86	0	73	0	0