Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	304116672	9075	0	0
TransStop_A	304116672	4601	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304116672	9075	0	0
T7	1175984	38	0	0
T8	298312	0	0	0
T11	12272	4	0	0
T12	14928	0	0	0
T32	23568	0	0	0
T33	12284	4	0	0
T34	8736	0	0	0
T35	12380	10	0	0
T36	17428	0	0	0
T37	0	46	0	0
T38	85540	19	0	0
T41	0	4	0	0
T42	0	42	0	0
T50	0	4	0	0
T126	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304116672	4601	0	0
T7	1175984	22	0	0
T8	298312	0	0	0
T11	12272	4	0	0
T12	14928	0	0	0
T32	23568	0	0	0
T33	12284	4	0	0
T34	8736	0	0	0
T35	12380	6	0	0
T36	17428	0	0	0
T37	0	23	0	0
T38	85540	7	0	0
T41	0	4	0	0
T42	0	17	0	0
T50	0	4	0	0
T126	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	76029168	2285	0	0
TransStop_A	76029168	1151	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76029168	2285	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	0	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2184	0	0	0
T35	3095	4	0	0
T36	4357	0	0	0
T37	0	13	0	0
T38	21385	2	0	0
T41	0	1	0	0
T42	0	10	0	0
T50	0	1	0	0
T126	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76029168	1151	0	0
T7	293996	6	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	0	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2184	0	0	0
T35	3095	2	0	0
T36	4357	0	0	0
T37	0	7	0	0
T38	21385	1	0	0
T41	0	1	0	0
T42	0	6	0	0
T50	0	1	0	0
T126	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	76029168	2295	0	0
TransStop_A	76029168	1155	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76029168	2295	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	0	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2184	0	0	0
T35	3095	3	0	0
T36	4357	0	0	0
T37	0	11	0	0
T38	21385	5	0	0
T41	0	1	0	0
T42	0	11	0	0
T50	0	1	0	0
T126	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76029168	1155	0	0
T7	293996	6	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	0	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2184	0	0	0
T35	3095	2	0	0
T36	4357	0	0	0
T37	0	5	0	0
T38	21385	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T50	0	1	0	0
T126	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	76029168	2258	0	0
TransStop_A	76029168	1141	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76029168	2258	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	0	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2184	0	0	0
T35	3095	2	0	0
T36	4357	0	0	0
T37	0	12	0	0
T38	21385	7	0	0
T41	0	1	0	0
T42	0	12	0	0
T50	0	1	0	0
T126	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76029168	1141	0	0
T7	293996	5	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	0	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2184	0	0	0
T35	3095	1	0	0
T36	4357	0	0	0
T37	0	5	0	0
T38	21385	3	0	0
T41	0	1	0	0
T42	0	5	0	0
T50	0	1	0	0
T126	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	76029168	2237	0	0
TransStop_A	76029168	1154	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76029168	2237	0	0
T7	293996	8	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	0	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2184	0	0	0
T35	3095	1	0	0
T36	4357	0	0	0
T37	0	10	0	0
T38	21385	5	0	0
T41	0	1	0	0
T42	0	9	0	0
T50	0	1	0	0
T126	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76029168	1154	0	0
T7	293996	5	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	0	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2184	0	0	0
T35	3095	1	0	0
T36	4357	0	0	0
T37	0	6	0	0
T38	21385	2	0	0
T41	0	1	0	0
T42	0	3	0	0
T50	0	1	0	0
T126	0	1	0	0