Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_div2.u_step_down_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T7,T32

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T7,T32
1	1	Covered	T10,T7,T32

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T7,T32
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	83464315	83461900	0	0
selKnown1	206414145	206411730	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	83464315	83461900	0	0
T7	311406	311403	0	0
T8	74975	74972	0	0
T10	13076	13073	0	0
T11	3617	3614	0	0
T12	4102	4099	0	0
T32	7363	7360	0	0
T33	3637	3634	0	0
T34	2525	2522	0	0
T35	3613	3610	0	0
T36	5180	5177	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	206414145	206411730	0	0
T7	777564	777561	0	0
T8	180219	180216	0	0
T10	22617	22614	0	0
T11	8835	8832	0	0
T12	10206	10203	0	0
T32	16968	16965	0	0
T33	8844	8841	0	0
T34	6285	6282	0	0
T35	8910	8907	0	0
T36	12546	12543	0	0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	33458774	33457969	0	0
selKnown1	68804715	68803910	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	33458774	33457969	0	0
T7	124765	124764	0	0
T8	29990	29989	0	0
T10	6245	6244	0	0
T11	1447	1446	0	0
T12	1641	1640	0	0
T32	3045	3044	0	0
T33	1455	1454	0	0
T34	1026	1025	0	0
T35	1445	1444	0	0
T36	2072	2071	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	68804715	68803910	0	0
T7	259188	259187	0	0
T8	60073	60072	0	0
T10	7539	7538	0	0
T11	2945	2944	0	0
T12	3402	3401	0	0
T32	5656	5655	0	0
T33	2948	2947	0	0
T34	2095	2094	0	0
T35	2970	2969	0	0
T36	4182	4181	0	0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T7,T32

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T7,T32
1	1	Covered	T10,T7,T32

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T7,T32
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	33276526	33275721	0	0
selKnown1	68804715	68803910	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	33276526	33275721	0	0
T7	124262	124261	0	0
T8	29990	29989	0	0
T10	3709	3708	0	0
T11	1447	1446	0	0
T12	1641	1640	0	0
T32	2795	2794	0	0
T33	1455	1454	0	0
T34	987	986	0	0
T35	1445	1444	0	0
T36	2072	2071	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	68804715	68803910	0	0
T7	259188	259187	0	0
T8	60073	60072	0	0
T10	7539	7538	0	0
T11	2945	2944	0	0
T12	3402	3401	0	0
T32	5656	5655	0	0
T33	2948	2947	0	0
T34	2095	2094	0	0
T35	2970	2969	0	0
T36	4182	4181	0	0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	16729015	16728210	0	0
selKnown1	68804715	68803910	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	16728210	0	0
T7	62379	62378	0	0
T8	14995	14994	0	0
T10	3122	3121	0	0
T11	723	722	0	0
T12	820	819	0	0
T32	1523	1522	0	0
T33	727	726	0	0
T34	512	511	0	0
T35	723	722	0	0
T36	1036	1035	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	68804715	68803910	0	0
T7	259188	259187	0	0
T8	60073	60072	0	0
T10	7539	7538	0	0
T11	2945	2944	0	0
T12	3402	3401	0	0
T32	5656	5655	0	0
T33	2948	2947	0	0
T34	2095	2094	0	0
T35	2970	2969	0	0
T36	4182	4181	0	0