Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	32601988	2506766	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	2506766	0	59
T1	0	24184	0	1
T2	0	19082	0	0
T3	0	51112	0	0
T7	149997	817	0	0
T8	16922	0	0	0
T9	0	880	0	1
T16	0	12954	0	1
T17	0	24918	0	0
T18	0	14452	0	0
T31	0	723	0	1
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	621	0	0
T38	2566	0	0	0
T49	835	0	0	0
T50	1481	0	0	0
T51	0	0	0	1
T127	0	0	0	1
T128	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1
T131	0	0	0	1