Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	33464451	502840	0	0
clk_enables_rd_A	33464451	6318	0	0
clk_hints_rd_A	33464451	5832	0	0
extclk_ctrl_rd_A	33464451	8037	0	0
extclk_ctrl_regwen_rd_A	33464451	4476	0	0
jitter_enable_rd_A	33464451	11149	0	0
jitter_regwen_rd_A	33464451	4435	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	502840	0	0
T7	149997	6305	0	0
T8	16922	0	0	0
T17	0	4957	0	0
T20	0	9283	0	0
T21	0	9064	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T38	2566	0	0	0
T47	0	5998	0	0
T48	0	10642	0	0
T49	835	0	0	0
T50	1481	0	0	0
T53	0	1033	0	0
T81	0	2907	0	0
T82	0	7386	0	0
T83	0	9123	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	6318	0	0
T3	608364	1	0	0
T16	211369	0	0	0
T17	0	236	0	0
T20	0	427	0	0
T47	0	216	0	0
T88	151375	0	0	0
T151	1504	9	0	0
T152	0	7	0	0
T153	0	1	0	0
T154	0	6	0	0
T155	0	9	0	0
T156	0	5	0	0
T157	1011	0	0	0
T158	2345	0	0	0
T159	1128	0	0	0
T160	1665	0	0	0
T161	1171	0	0	0
T162	1511	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	5832	0	0
T17	162468	179	0	0
T18	213584	0	0	0
T19	126890	0	0	0
T20	0	352	0	0
T47	0	169	0	0
T52	806	0	0	0
T130	0	4	0	0
T151	1504	4	0	0
T152	1816	0	0	0
T154	0	7	0	0
T155	0	7	0	0
T156	0	7	0	0
T161	1171	0	0	0
T162	1511	0	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	1867	0	0	0
T166	3037	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	8037	0	0
T3	0	141	0	0
T4	106039	0	0	0
T5	0	9	0	0
T6	0	9	0	0
T9	38579	0	0	0
T17	0	171	0	0
T34	2095	23	0	0
T35	1546	0	0	0
T36	915	0	0	0
T38	2566	0	0	0
T39	1074	0	0	0
T40	2398	0	0	0
T49	835	0	0	0
T50	1481	0	0	0
T84	0	39	0	0
T125	0	32	0	0
T167	0	25	0	0
T168	0	31	0	0
T169	0	32	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	4476	0	0
T5	17778	4	0	0
T17	0	155	0	0
T20	0	307	0	0
T43	820	0	0	0
T44	24562	0	0	0
T45	62718	0	0	0
T47	0	153	0	0
T56	1520	0	0	0
T71	0	29	0	0
T84	2140	0	0	0
T85	1934	0	0	0
T86	1306	0	0	0
T87	1585	0	0	0
T89	0	13	0	0
T125	0	21	0	0
T167	1668	0	0	0
T170	0	27	0	0
T171	0	33	0	0
T172	0	8	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	11149	0	0
T3	0	124	0	0
T5	17778	0	0	0
T17	0	292	0	0
T20	0	363	0	0
T41	2258	79	0	0
T42	3866	0	0	0
T43	820	0	0	0
T44	24562	0	0	0
T47	0	305	0	0
T56	1520	0	0	0
T84	2140	0	0	0
T85	1934	0	0	0
T86	1306	0	0	0
T87	1585	0	0	0
T151	0	57	0	0
T152	0	82	0	0
T153	0	103	0	0
T154	0	221	0	0
T155	0	82	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	4435	0	0
T17	162468	200	0	0
T18	213584	0	0	0
T19	126890	0	0	0
T20	0	381	0	0
T47	0	169	0	0
T52	806	0	0	0
T89	97856	0	0	0
T152	1816	0	0	0
T165	1867	0	0	0
T166	3037	0	0	0
T173	0	245	0	0
T174	0	258	0	0
T175	0	64	0	0
T176	0	235	0	0
T177	0	109	0	0
T178	0	397	0	0
T179	0	170	0	0
T180	1005	0	0	0
T181	22528	0	0	0