Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T7
1	0	Covered	T10,T7,T32
1	1	Covered	T10,T7,T32

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	68805145	2796	0	0
g_div2.Div2Whole_A	68805145	3281	0	0
g_div4.Div4Stepped_A	33459182	2742	0	0
g_div4.Div4Whole_A	33459182	3146	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68805145	2796	0	0
T7	259188	16	0	0
T8	60074	0	0	0
T10	7540	10	0	0
T11	2945	0	0	0
T12	3403	0	0	0
T32	5657	4	0	0
T33	2949	0	0	0
T34	2096	2	0	0
T35	2971	0	0	0
T36	4182	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	11	0	0
T84	0	8	0	0
T85	0	1	0	0
T86	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68805145	3281	0	0
T7	259188	21	0	0
T8	60074	0	0	0
T10	7540	9	0	0
T11	2945	0	0	0
T12	3403	0	0	0
T32	5657	4	0	0
T33	2949	0	0	0
T34	2096	5	0	0
T35	2971	0	0	0
T36	4182	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	11	0	0
T84	0	9	0	0
T85	0	8	0	0
T86	0	3	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33459182	2742	0	0
T7	124766	15	0	0
T8	29991	0	0	0
T10	6246	10	0	0
T11	1447	0	0	0
T12	1641	0	0	0
T32	3046	4	0	0
T33	1455	0	0	0
T34	1027	2	0	0
T35	1446	0	0	0
T36	2072	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	11	0	0
T84	0	8	0	0
T85	0	1	0	0
T86	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33459182	3146	0	0
T7	124766	21	0	0
T8	29991	0	0	0
T10	6246	9	0	0
T11	1447	0	0	0
T12	1641	0	0	0
T32	3046	4	0	0
T33	1455	0	0	0
T34	1027	5	0	0
T35	1446	0	0	0
T36	2072	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	11	0	0
T84	0	9	0	0
T85	0	6	0	0
T86	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T7
1	0	Covered	T10,T7,T32
1	1	Covered	T10,T7,T32

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	68805145	2796	0	0
g_div2.Div2Whole_A	68805145	3281	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68805145	2796	0	0
T7	259188	16	0	0
T8	60074	0	0	0
T10	7540	10	0	0
T11	2945	0	0	0
T12	3403	0	0	0
T32	5657	4	0	0
T33	2949	0	0	0
T34	2096	2	0	0
T35	2971	0	0	0
T36	4182	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	11	0	0
T84	0	8	0	0
T85	0	1	0	0
T86	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68805145	3281	0	0
T7	259188	21	0	0
T8	60074	0	0	0
T10	7540	9	0	0
T11	2945	0	0	0
T12	3403	0	0	0
T32	5657	4	0	0
T33	2949	0	0	0
T34	2096	5	0	0
T35	2971	0	0	0
T36	4182	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	11	0	0
T84	0	9	0	0
T85	0	8	0	0
T86	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T7
1	0	Covered	T10,T7,T32
1	1	Covered	T10,T7,T32

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	33459182	2742	0	0
g_div4.Div4Whole_A	33459182	3146	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33459182	2742	0	0
T7	124766	15	0	0
T8	29991	0	0	0
T10	6246	10	0	0
T11	1447	0	0	0
T12	1641	0	0	0
T32	3046	4	0	0
T33	1455	0	0	0
T34	1027	2	0	0
T35	1446	0	0	0
T36	2072	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	11	0	0
T84	0	8	0	0
T85	0	1	0	0
T86	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33459182	3146	0	0
T7	124766	21	0	0
T8	29991	0	0	0
T10	6246	9	0	0
T11	1447	0	0	0
T12	1641	0	0	0
T32	3046	4	0	0
T33	1455	0	0	0
T34	1027	5	0	0
T35	1446	0	0	0
T36	2072	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	11	0	0
T84	0	9	0	0
T85	0	6	0	0
T86	0	3	0	0