Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	97805964	430	0	0
StatusRise_A	97805964	430	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97805964	430	0	0
T7	449991	0	0	0
T8	50766	0	0	0
T12	3147	12	0	0
T30	0	1	0	0
T32	4239	0	0	0
T33	4515	0	0	0
T34	6285	0	0	0
T35	4638	0	0	0
T36	2745	0	0	0
T38	7698	0	0	0
T49	2505	0	0	0
T56	0	13	0	0
T57	0	7	0	0
T157	0	7	0	0
T180	0	12	0	0
T182	0	9	0	0
T183	0	14	0	0
T184	0	7	0	0
T185	0	14	0	0
T186	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97805964	430	0	0
T7	449991	0	0	0
T8	50766	0	0	0
T12	3147	12	0	0
T30	0	1	0	0
T32	4239	0	0	0
T33	4515	0	0	0
T34	6285	0	0	0
T35	4638	0	0	0
T36	2745	0	0	0
T38	7698	0	0	0
T49	2505	0	0	0
T56	0	13	0	0
T57	0	7	0	0
T157	0	7	0	0
T180	0	12	0	0
T182	0	9	0	0
T183	0	14	0	0
T184	0	7	0	0
T185	0	14	0	0
T186	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	32601988	138	0	0
StatusRise_A	32601988	138	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	138	0	0
T7	149997	0	0	0
T8	16922	0	0	0
T12	1049	3	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T38	2566	0	0	0
T49	835	0	0	0
T56	0	6	0	0
T57	0	2	0	0
T157	0	2	0	0
T180	0	4	0	0
T182	0	2	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0
T186	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	138	0	0
T7	149997	0	0	0
T8	16922	0	0	0
T12	1049	3	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T38	2566	0	0	0
T49	835	0	0	0
T56	0	6	0	0
T57	0	2	0	0
T157	0	2	0	0
T180	0	4	0	0
T182	0	2	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0
T186	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	32601988	148	0	0
StatusRise_A	32601988	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	148	0	0
T7	149997	0	0	0
T8	16922	0	0	0
T12	1049	4	0	0
T30	0	1	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T38	2566	0	0	0
T49	835	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	148	0	0
T7	149997	0	0	0
T8	16922	0	0	0
T12	1049	4	0	0
T30	0	1	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T38	2566	0	0	0
T49	835	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	32601988	144	0	0
StatusRise_A	32601988	144	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	144	0	0
T7	149997	0	0	0
T8	16922	0	0	0
T12	1049	5	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T38	2566	0	0	0
T49	835	0	0	0
T56	0	4	0	0
T57	0	3	0	0
T157	0	2	0	0
T180	0	3	0	0
T182	0	3	0	0
T183	0	4	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32601988	144	0	0
T7	149997	0	0	0
T8	16922	0	0	0
T12	1049	5	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T38	2566	0	0	0
T49	835	0	0	0
T56	0	4	0	0
T57	0	3	0	0
T157	0	2	0	0
T180	0	3	0	0
T182	0	3	0	0
T183	0	4	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0