Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	800615018	30834	0	0
CgEnOn_A	800615018	21690	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	800615018	30834	0	0
T7	3046358	95	0	0
T8	753408	3	0	0
T10	20676	3	0	0
T11	18860	7	0	0
T12	39196	38	0	0
T30	0	5	0	0
T32	64502	3	0	0
T33	33088	6	0	0
T34	23482	3	0	0
T35	33262	7	0	0
T36	46970	45	0	0
T38	184623	2	0	0
T49	29699	0	0	0
T50	0	1	0	0
T56	0	15	0	0
T57	0	10	0	0
T81	0	5	0	0
T157	0	15	0	0
T180	0	25	0	0
T182	0	20	0	0
T183	0	25	0	0
T184	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	800615018	21690	0	0
T7	3046358	77	0	0
T8	753408	0	0	0
T11	18860	4	0	0
T12	39196	35	0	0
T30	0	6	0	0
T32	64502	0	0	0
T33	33088	3	0	0
T34	23482	0	0	0
T35	33262	4	0	0
T36	46970	42	0	0
T37	0	91	0	0
T38	230732	0	0	0
T41	0	4	0	0
T43	0	13	0	0
T49	29699	0	0	0
T50	0	2	0	0
T56	0	24	0	0
T57	0	10	0	0
T81	0	4	0	0
T126	0	2	0	0
T157	0	15	0	0
T180	0	25	0	0
T182	0	20	0	0
T183	0	25	0	0
T184	0	10	0	0
T185	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Unreachable
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	33458774	161	0	0
CgEnOn_A	33458774	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33458774	161	0	0
T7	124765	0	0	0
T8	29990	0	0	0
T12	1641	4	0	0
T30	0	1	0	0
T32	3045	0	0	0
T33	1455	0	0	0
T34	1026	0	0	0
T35	1445	0	0	0
T36	2072	0	0	0
T38	10211	0	0	0
T49	3043	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33458774	161	0	0
T7	124765	0	0	0
T8	29990	0	0	0
T12	1641	4	0	0
T30	0	1	0	0
T32	3045	0	0	0
T33	1455	0	0	0
T34	1026	0	0	0
T35	1445	0	0	0
T36	2072	0	0	0
T38	10211	0	0	0
T49	3043	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Unreachable
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16729015	161	0	0
CgEnOn_A	16729015	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	161	0	0
T7	62379	0	0	0
T8	14995	0	0	0
T12	820	4	0	0
T30	0	1	0	0
T32	1523	0	0	0
T33	727	0	0	0
T34	512	0	0	0
T35	723	0	0	0
T36	1036	0	0	0
T38	5105	0	0	0
T49	1521	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	161	0	0
T7	62379	0	0	0
T8	14995	0	0	0
T12	820	4	0	0
T30	0	1	0	0
T32	1523	0	0	0
T33	727	0	0	0
T34	512	0	0	0
T35	723	0	0	0
T36	1036	0	0	0
T38	5105	0	0	0
T49	1521	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Unreachable
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16729015	161	0	0
CgEnOn_A	16729015	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	161	0	0
T7	62379	0	0	0
T8	14995	0	0	0
T12	820	4	0	0
T30	0	1	0	0
T32	1523	0	0	0
T33	727	0	0	0
T34	512	0	0	0
T35	723	0	0	0
T36	1036	0	0	0
T38	5105	0	0	0
T49	1521	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	161	0	0
T7	62379	0	0	0
T8	14995	0	0	0
T12	820	4	0	0
T30	0	1	0	0
T32	1523	0	0	0
T33	727	0	0	0
T34	512	0	0	0
T35	723	0	0	0
T36	1036	0	0	0
T38	5105	0	0	0
T49	1521	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Unreachable
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16729015	161	0	0
CgEnOn_A	16729015	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	161	0	0
T7	62379	0	0	0
T8	14995	0	0	0
T12	820	4	0	0
T30	0	1	0	0
T32	1523	0	0	0
T33	727	0	0	0
T34	512	0	0	0
T35	723	0	0	0
T36	1036	0	0	0
T38	5105	0	0	0
T49	1521	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	161	0	0
T7	62379	0	0	0
T8	14995	0	0	0
T12	820	4	0	0
T30	0	1	0	0
T32	1523	0	0	0
T33	727	0	0	0
T34	512	0	0	0
T35	723	0	0	0
T36	1036	0	0	0
T38	5105	0	0	0
T49	1521	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Unreachable
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	68804715	161	0	0
CgEnOn_A	68804715	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68804715	161	0	0
T7	259188	0	0	0
T8	60073	0	0	0
T12	3402	4	0	0
T30	0	1	0	0
T32	5656	0	0	0
T33	2948	0	0	0
T34	2095	0	0	0
T35	2970	0	0	0
T36	4182	0	0	0
T38	20528	0	0	0
T49	6165	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T81	0	1	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68804715	152	0	0
T7	259188	0	0	0
T8	60073	0	0	0
T12	3402	4	0	0
T30	0	1	0	0
T32	5656	0	0	0
T33	2948	0	0	0
T34	2095	0	0	0
T35	2970	0	0	0
T36	4182	0	0	0
T38	20528	0	0	0
T49	6165	0	0	0
T56	0	3	0	0
T57	0	2	0	0
T157	0	3	0	0
T180	0	5	0	0
T182	0	4	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Unreachable
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76028694	142	0	0
CgEnOn_A	76028694	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	142	0	0
T7	293996	0	0	0
T8	74578	0	0	0
T12	3732	3	0	0
T21	0	1	0	0
T32	5892	0	0	0
T33	3071	0	0	0
T34	2183	0	0	0
T35	3095	0	0	0
T36	4356	0	0	0
T38	21384	0	0	0
T49	6423	0	0	0
T56	0	6	0	0
T57	0	2	0	0
T157	0	2	0	0
T180	0	4	0	0
T182	0	2	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	138	0	0
T7	293996	0	0	0
T8	74578	0	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	0	0	0
T34	2183	0	0	0
T35	3095	0	0	0
T36	4356	0	0	0
T38	21384	0	0	0
T49	6423	0	0	0
T56	0	6	0	0
T57	0	2	0	0
T157	0	2	0	0
T180	0	4	0	0
T182	0	2	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0
T186	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Unreachable
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76028694	142	0	0
CgEnOn_A	76028694	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	142	0	0
T7	293996	0	0	0
T8	74578	0	0	0
T12	3732	3	0	0
T21	0	1	0	0
T32	5892	0	0	0
T33	3071	0	0	0
T34	2183	0	0	0
T35	3095	0	0	0
T36	4356	0	0	0
T38	21384	0	0	0
T49	6423	0	0	0
T56	0	6	0	0
T57	0	2	0	0
T157	0	2	0	0
T180	0	4	0	0
T182	0	2	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	138	0	0
T7	293996	0	0	0
T8	74578	0	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	0	0	0
T34	2183	0	0	0
T35	3095	0	0	0
T36	4356	0	0	0
T38	21384	0	0	0
T49	6423	0	0	0
T56	0	6	0	0
T57	0	2	0	0
T157	0	2	0	0
T180	0	4	0	0
T182	0	2	0	0
T183	0	5	0	0
T184	0	2	0	0
T185	0	5	0	0
T186	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Unreachable
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36499908	149	0	0
CgEnOn_A	36499908	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499908	149	0	0
T7	132480	0	0	0
T8	32917	0	0	0
T12	1719	5	0	0
T32	2828	0	0	0
T33	1474	0	0	0
T34	1047	0	0	0
T35	1485	0	0	0
T36	2091	0	0	0
T38	10265	0	0	0
T47	0	1	0	0
T49	3082	0	0	0
T56	0	4	0	0
T57	0	3	0	0
T157	0	2	0	0
T180	0	3	0	0
T182	0	3	0	0
T183	0	4	0	0
T184	0	3	0	0
T185	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499908	146	0	0
T7	132480	0	0	0
T8	32917	0	0	0
T12	1719	5	0	0
T32	2828	0	0	0
T33	1474	0	0	0
T34	1047	0	0	0
T35	1485	0	0	0
T36	2091	0	0	0
T38	10265	0	0	0
T47	0	1	0	0
T49	3082	0	0	0
T56	0	4	0	0
T57	0	3	0	0
T157	0	2	0	0
T180	0	3	0	0
T182	0	3	0	0
T183	0	4	0	0
T184	0	3	0	0
T185	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T56,T30
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16729015	4994	0	0
CgEnOn_A	16729015	2722	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	4994	0	0
T7	62379	27	0	0
T8	14995	1	0	0
T10	3122	1	0	0
T11	723	2	0	0
T12	820	5	0	0
T32	1523	1	0	0
T33	727	1	0	0
T34	512	1	0	0
T35	723	1	0	0
T36	1036	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16729015	2722	0	0
T7	62379	21	0	0
T8	14995	0	0	0
T11	723	1	0	0
T12	820	4	0	0
T30	0	1	0	0
T32	1523	0	0	0
T33	727	0	0	0
T34	512	0	0	0
T35	723	0	0	0
T36	1036	14	0	0
T37	0	28	0	0
T38	5105	0	0	0
T41	0	1	0	0
T43	0	4	0	0
T56	0	3	0	0
T126	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T56,T30
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	33458774	5001	0	0
CgEnOn_A	33458774	2729	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33458774	5001	0	0
T7	124765	29	0	0
T8	29990	1	0	0
T10	6245	1	0	0
T11	1447	2	0	0
T12	1641	5	0	0
T32	3045	1	0	0
T33	1455	2	0	0
T34	1026	1	0	0
T35	1445	1	0	0
T36	2072	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33458774	2729	0	0
T7	124765	23	0	0
T8	29990	0	0	0
T11	1447	1	0	0
T12	1641	4	0	0
T32	3045	0	0	0
T33	1455	1	0	0
T34	1026	0	0	0
T35	1445	0	0	0
T36	2072	14	0	0
T37	0	25	0	0
T38	10211	0	0	0
T41	0	1	0	0
T43	0	4	0	0
T56	0	3	0	0
T126	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T56,T30
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	68804715	4984	0	0
CgEnOn_A	68804715	2703	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68804715	4984	0	0
T7	259188	29	0	0
T8	60073	1	0	0
T10	7539	1	0	0
T11	2945	2	0	0
T12	3402	5	0	0
T32	5656	1	0	0
T33	2948	2	0	0
T34	2095	1	0	0
T35	2970	1	0	0
T36	4182	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68804715	2703	0	0
T7	259188	23	0	0
T8	60073	0	0	0
T11	2945	1	0	0
T12	3402	4	0	0
T32	5656	0	0	0
T33	2948	1	0	0
T34	2095	0	0	0
T35	2970	0	0	0
T36	4182	14	0	0
T37	0	25	0	0
T38	20528	0	0	0
T41	0	1	0	0
T43	0	5	0	0
T50	0	1	0	0
T56	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T56,T57
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36499908	4974	0	0
CgEnOn_A	36499908	2691	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499908	4974	0	0
T7	132480	28	0	0
T8	32917	1	0	0
T10	3770	1	0	0
T11	1473	2	0	0
T12	1719	6	0	0
T32	2828	1	0	0
T33	1474	2	0	0
T34	1047	1	0	0
T35	1485	1	0	0
T36	2091	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499908	2691	0	0
T7	132480	22	0	0
T8	32917	0	0	0
T11	1473	1	0	0
T12	1719	5	0	0
T32	2828	0	0	0
T33	1474	1	0	0
T34	1047	0	0	0
T35	1485	0	0	0
T36	2091	12	0	0
T37	0	25	0	0
T38	10265	0	0	0
T41	0	1	0	0
T43	0	4	0	0
T56	0	4	0	0
T126	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Covered	T11,T7,T33
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76028694	2427	0	0
CgEnOn_A	76028694	2423	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	2427	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2183	0	0	0
T35	3095	4	0	0
T36	4356	0	0	0
T37	0	13	0	0
T38	21384	2	0	0
T41	0	1	0	0
T42	0	10	0	0
T50	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	2423	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2183	0	0	0
T35	3095	4	0	0
T36	4356	0	0	0
T37	0	13	0	0
T38	21384	2	0	0
T41	0	1	0	0
T42	0	10	0	0
T50	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Covered	T11,T7,T33
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76028694	2437	0	0
CgEnOn_A	76028694	2433	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	2437	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2183	0	0	0
T35	3095	3	0	0
T36	4356	0	0	0
T37	0	11	0	0
T38	21384	5	0	0
T41	0	1	0	0
T42	0	11	0	0
T50	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	2433	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2183	0	0	0
T35	3095	3	0	0
T36	4356	0	0	0
T37	0	11	0	0
T38	21384	5	0	0
T41	0	1	0	0
T42	0	11	0	0
T50	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Covered	T11,T7,T33
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76028694	2400	0	0
CgEnOn_A	76028694	2396	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	2400	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2183	0	0	0
T35	3095	2	0	0
T36	4356	0	0	0
T37	0	12	0	0
T38	21384	7	0	0
T41	0	1	0	0
T42	0	12	0	0
T50	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	2396	0	0
T7	293996	10	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2183	0	0	0
T35	3095	2	0	0
T36	4356	0	0	0
T37	0	12	0	0
T38	21384	7	0	0
T41	0	1	0	0
T42	0	12	0	0
T50	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T12,T7,T4
1	0	Covered	T11,T7,T33
1	1	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76028694	2379	0	0
CgEnOn_A	76028694	2375	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	2379	0	0
T7	293996	8	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2183	0	0	0
T35	3095	1	0	0
T36	4356	0	0	0
T37	0	10	0	0
T38	21384	5	0	0
T41	0	1	0	0
T42	0	9	0	0
T50	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76028694	2375	0	0
T7	293996	8	0	0
T8	74578	0	0	0
T11	3068	1	0	0
T12	3732	3	0	0
T32	5892	0	0	0
T33	3071	1	0	0
T34	2183	0	0	0
T35	3095	1	0	0
T36	4356	0	0	0
T37	0	10	0	0
T38	21384	5	0	0
T41	0	1	0	0
T42	0	9	0	0
T50	0	1	0	0