Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
54.76 41.92 57.65 81.32 0.00 48.71 89.43 64.27


Total tests in report: 205
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
51.88 51.88 41.22 41.22 51.23 51.23 91.12 91.12 0.00 0.00 48.55 48.55 82.99 82.99 48.03 48.03 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.439859682
54.16 2.28 41.52 0.31 53.82 2.58 91.76 0.64 0.00 0.00 48.65 0.10 86.44 3.45 56.92 8.89 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1307907349
55.06 0.90 41.64 0.12 55.59 1.78 91.76 0.00 0.00 0.00 48.65 0.00 88.97 2.53 58.80 1.88 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1291510106
55.63 0.57 41.74 0.09 56.28 0.69 91.76 0.00 0.00 0.00 48.71 0.05 89.20 0.23 61.71 2.91 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3385920043
55.90 0.27 41.74 0.00 56.28 0.00 92.12 0.37 0.00 0.00 48.71 0.00 89.20 0.00 63.25 1.54 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.2876865019
55.99 0.09 41.74 0.00 56.68 0.40 92.12 0.00 0.00 0.00 48.71 0.00 89.43 0.23 63.25 0.00 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.489697458
56.07 0.08 41.90 0.16 56.88 0.20 92.12 0.00 0.00 0.00 48.71 0.00 89.43 0.00 63.42 0.17 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1205541770
56.13 0.07 41.90 0.00 57.00 0.12 92.12 0.00 0.00 0.00 48.71 0.00 89.43 0.00 63.76 0.34 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1561878484
56.19 0.06 41.92 0.02 57.00 0.00 92.49 0.37 0.00 0.00 48.71 0.00 89.43 0.00 63.76 0.00 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1622304961
56.24 0.05 41.92 0.00 57.00 0.00 92.49 0.00 0.00 0.00 48.71 0.00 89.43 0.00 64.10 0.34 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.424587284
56.27 0.03 41.92 0.00 57.25 0.24 92.49 0.00 0.00 0.00 48.71 0.00 89.43 0.00 64.10 0.00 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3535321024
56.30 0.02 41.92 0.00 57.25 0.00 92.49 0.00 0.00 0.00 48.71 0.00 89.43 0.00 64.27 0.17 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1751127890
56.31 0.01 41.92 0.00 57.33 0.08 92.49 0.00 0.00 0.00 48.71 0.00 89.43 0.00 64.27 0.00 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2879558168
56.32 0.01 41.92 0.00 57.41 0.08 92.49 0.00 0.00 0.00 48.71 0.00 89.43 0.00 64.27 0.00 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1199458807
56.32 0.01 41.92 0.00 57.45 0.04 92.49 0.00 0.00 0.00 48.71 0.00 89.43 0.00 64.27 0.00 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1784602442

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2682291656
/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1274230318
/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1006802313
/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1869729148
/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1707501024
/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.4000096012
/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.698923459
/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.451286743
/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.131977698
/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2648757618
/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.587653121
/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1223765310
/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2691924478
/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.8849456
/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3855780276
/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3373235802
/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.4037122366
/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2312891739
/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.677774175
/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2327135125
/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.1022449719
/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1414417684
/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.3268277387
/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3088888148
/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3120943491
/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2102994961
/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3867881355
/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.4224192143
/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2073492344
/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3170870520
/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2295728395
/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2435266799
/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2097268705
/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.552590848
/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.4162864885
/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2550802585
/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.4071422023
/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3752330515
/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3777360759
/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1803302326
/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.3355189659
/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2792256198
/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.799516332
/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2122034450
/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2743662727
/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1740849097
/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2470797147
/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.527978457
/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1994429444
/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2855877862
/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1216120262
/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2536717725
/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.620475304
/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.437987659
/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.463336265
/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4220451108
/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2570348370
/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3445384516
/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3647895292
/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3329491142
/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2821632665
/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3517096482
/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3403682010
/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3066855718
/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2263475361
/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.985069252
/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.795332994
/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2931571567
/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2927182484
/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1052117283
/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1420267158
/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.882011293
/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2087821937
/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1095249603
/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3644714727
/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.514060217
/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.945768198
/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.288118828
/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2275332432
/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2095119893
/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.895798287
/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3383539930
/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3020832489
/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1705511728
/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2519789988
/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1416926579
/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3161052057
/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1430657800
/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.4291023942
/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2665718381
/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1287688242
/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.216844871
/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1956308288
/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2854321868
/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.724946414
/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.1357555644
/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1164772816
/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2019678561
/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3138829702
/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.12934459
/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.66081907
/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2390999827
/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3068638955
/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3829938406
/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.716314643
/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3867493852
/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.1747267126
/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1322757506
/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3924848601
/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.282252023
/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.4201820677
/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3779725906
/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2232653743
/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2130900160
/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.687533297
/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2329712359
/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.374761157
/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.20135537
/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2094220507
/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4124466307
/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2224888333
/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.88851607
/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2371950720
/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3589701149
/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1092593494
/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2182100245
/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.297070107
/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1304388579
/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1273260715
/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3232151289
/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.817730767
/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.724604308
/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2931987127
/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1078588207
/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.445503074
/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2689361382
/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1534734052
/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1750672672
/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2186857311
/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3615946768
/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.4071068132
/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1425030782
/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3166059049
/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2283867952
/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.669586157
/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1976361867
/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.341244214
/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4001865884
/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2525733017
/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.280244620
/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1905681881
/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2141469548
/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1144326306
/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2661928636
/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3581336642
/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2694488047
/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2190319976
/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1945833201
/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1787689106
/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.301138117
/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.3886252083
/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2866071515
/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.4244004925
/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1485467047
/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.251127440
/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.356967235
/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1359218533
/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2107262034
/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.142467918
/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3984608029
/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2823140183
/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3407567448
/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.975185572
/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2599142150
/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3646562938
/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3996574015
/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3230441497
/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.559962693
/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1213210807
/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1039648458
/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3451489508
/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.282633276
/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1232265013
/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2228174975
/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1281203627
/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2316300505
/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2051107772
/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.442190764
/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.4283266875
/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2002784572



Total test records in report: 205
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.439859682 Aug 14 04:28:28 PM PDT 24 Aug 14 04:28:31 PM PDT 24 129071450 ps
T2 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.4037122366 Aug 14 04:28:30 PM PDT 24 Aug 14 04:28:31 PM PDT 24 46443713 ps
T3 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3166059049 Aug 14 04:28:34 PM PDT 24 Aug 14 04:28:35 PM PDT 24 58527040 ps
T6 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3855780276 Aug 14 04:28:28 PM PDT 24 Aug 14 04:28:29 PM PDT 24 59569155 ps
T9 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3329491142 Aug 14 04:28:50 PM PDT 24 Aug 14 04:28:51 PM PDT 24 15686735 ps
T4 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3644714727 Aug 14 04:28:42 PM PDT 24 Aug 14 04:28:44 PM PDT 24 33303258 ps
T5 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3120943491 Aug 14 04:28:37 PM PDT 24 Aug 14 04:28:39 PM PDT 24 86727475 ps
T8 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3385920043 Aug 14 04:28:42 PM PDT 24 Aug 14 04:28:45 PM PDT 24 85016277 ps
T16 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1307907349 Aug 14 04:28:40 PM PDT 24 Aug 14 04:28:42 PM PDT 24 137213151 ps
T7 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3646562938 Aug 14 04:28:37 PM PDT 24 Aug 14 04:28:38 PM PDT 24 21510416 ps
T17 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1751127890 Aug 14 04:28:15 PM PDT 24 Aug 14 04:28:17 PM PDT 24 69371060 ps
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T151 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1414417684 Aug 14 04:28:50 PM PDT 24 Aug 14 04:28:51 PM PDT 24 22049912 ps
T152 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.131977698 Aug 14 04:28:25 PM PDT 24 Aug 14 04:28:27 PM PDT 24 160129088 ps
T153 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.437987659 Aug 14 04:28:47 PM PDT 24 Aug 14 04:28:49 PM PDT 24 65683708 ps
T154 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1994429444 Aug 14 04:28:34 PM PDT 24 Aug 14 04:28:35 PM PDT 24 302707486 ps
T155 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2102994961 Aug 14 04:28:30 PM PDT 24 Aug 14 04:28:33 PM PDT 24 118713761 ps
T156 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2866071515 Aug 14 04:28:32 PM PDT 24 Aug 14 04:28:33 PM PDT 24 10954088 ps
T157 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3924848601 Aug 14 04:28:41 PM PDT 24 Aug 14 04:28:42 PM PDT 24 15181387 ps
T158 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.4071422023 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:23 PM PDT 24 28702142 ps
T159 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2879558168 Aug 14 04:28:39 PM PDT 24 Aug 14 04:28:40 PM PDT 24 56554777 ps
T160 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1750672672 Aug 14 04:28:40 PM PDT 24 Aug 14 04:28:41 PM PDT 24 30063376 ps
T161 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1803302326 Aug 14 04:28:43 PM PDT 24 Aug 14 04:28:46 PM PDT 24 166268162 ps
T162 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.895798287 Aug 14 04:28:41 PM PDT 24 Aug 14 04:28:45 PM PDT 24 259776529 ps
T44 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2002784572 Aug 14 04:28:41 PM PDT 24 Aug 14 04:28:44 PM PDT 24 411722364 ps
T163 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.88851607 Aug 14 04:28:16 PM PDT 24 Aug 14 04:28:18 PM PDT 24 114302851 ps
T164 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1144326306 Aug 14 04:28:33 PM PDT 24 Aug 14 04:28:34 PM PDT 24 48354171 ps
T165 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.698923459 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:28 PM PDT 24 48689440 ps
T80 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.2876865019 Aug 14 04:28:42 PM PDT 24 Aug 14 04:28:44 PM PDT 24 136000362 ps
T166 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2095119893 Aug 14 04:28:33 PM PDT 24 Aug 14 04:28:35 PM PDT 24 129419136 ps
T167 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2743662727 Aug 14 04:28:35 PM PDT 24 Aug 14 04:28:37 PM PDT 24 78652553 ps
T168 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3170870520 Aug 14 04:28:25 PM PDT 24 Aug 14 04:28:26 PM PDT 24 59963723 ps
T169 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3517096482 Aug 14 04:28:45 PM PDT 24 Aug 14 04:28:47 PM PDT 24 152264909 ps
T82 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2665718381 Aug 14 04:28:39 PM PDT 24 Aug 14 04:28:41 PM PDT 24 98458614 ps
T170 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.280244620 Aug 14 04:29:10 PM PDT 24 Aug 14 04:29:11 PM PDT 24 77693512 ps
T171 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2094220507 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:25 PM PDT 24 68500461 ps
T172 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2097268705 Aug 14 04:28:54 PM PDT 24 Aug 14 04:28:57 PM PDT 24 304950511 ps
T173 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.4162864885 Aug 14 04:28:36 PM PDT 24 Aug 14 04:28:37 PM PDT 24 69015872 ps
T174 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1322757506 Aug 14 04:28:34 PM PDT 24 Aug 14 04:28:35 PM PDT 24 31920661 ps
T175 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2141469548 Aug 14 04:28:56 PM PDT 24 Aug 14 04:28:57 PM PDT 24 38783198 ps
T176 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2691924478 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:27 PM PDT 24 16512007 ps
T177 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.514060217 Aug 14 04:28:53 PM PDT 24 Aug 14 04:28:54 PM PDT 24 15227939 ps
T178 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1287688242 Aug 14 04:28:15 PM PDT 24 Aug 14 04:28:16 PM PDT 24 92556823 ps
T179 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.552590848 Aug 14 04:28:35 PM PDT 24 Aug 14 04:28:37 PM PDT 24 53799442 ps
T180 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1304388579 Aug 14 04:28:55 PM PDT 24 Aug 14 04:28:55 PM PDT 24 40831810 ps
T181 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.142467918 Aug 14 04:28:50 PM PDT 24 Aug 14 04:28:51 PM PDT 24 38983580 ps
T182 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3230441497 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:27 PM PDT 24 14506406 ps
T46 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2327135125 Aug 14 04:28:25 PM PDT 24 Aug 14 04:28:28 PM PDT 24 425584353 ps
T183 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.4224192143 Aug 14 04:28:29 PM PDT 24 Aug 14 04:28:29 PM PDT 24 20359108 ps
T184 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.12934459 Aug 14 04:28:25 PM PDT 24 Aug 14 04:28:28 PM PDT 24 73912138 ps
T185 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.297070107 Aug 14 04:28:39 PM PDT 24 Aug 14 04:28:40 PM PDT 24 13113705 ps
T186 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1425030782 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:25 PM PDT 24 142167691 ps
T187 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.795332994 Aug 14 04:28:35 PM PDT 24 Aug 14 04:28:37 PM PDT 24 54375965 ps
T188 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.451286743 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:28 PM PDT 24 64888535 ps
T189 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4124466307 Aug 14 04:28:20 PM PDT 24 Aug 14 04:28:22 PM PDT 24 142271320 ps
T190 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2122034450 Aug 14 04:28:36 PM PDT 24 Aug 14 04:28:37 PM PDT 24 36978905 ps
T191 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.4000096012 Aug 14 04:28:29 PM PDT 24 Aug 14 04:28:30 PM PDT 24 14719479 ps
T192 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3020832489 Aug 14 04:28:50 PM PDT 24 Aug 14 04:28:53 PM PDT 24 305612329 ps
T193 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3232151289 Aug 14 04:28:38 PM PDT 24 Aug 14 04:28:38 PM PDT 24 13044033 ps
T194 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2648757618 Aug 14 04:28:41 PM PDT 24 Aug 14 04:28:43 PM PDT 24 61846498 ps
T195 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4001865884 Aug 14 04:29:20 PM PDT 24 Aug 14 04:29:21 PM PDT 24 26395005 ps
T196 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4220451108 Aug 14 04:28:36 PM PDT 24 Aug 14 04:28:37 PM PDT 24 16926810 ps
T197 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.559962693 Aug 14 04:28:24 PM PDT 24 Aug 14 04:28:25 PM PDT 24 34955057 ps
T198 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2232653743 Aug 14 04:29:40 PM PDT 24 Aug 14 04:29:48 PM PDT 24 845166823 ps
T199 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2689361382 Aug 14 04:28:46 PM PDT 24 Aug 14 04:28:47 PM PDT 24 24321416 ps
T200 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.799516332 Aug 14 04:29:36 PM PDT 24 Aug 14 04:29:37 PM PDT 24 46798982 ps
T201 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2316300505 Aug 14 04:28:35 PM PDT 24 Aug 14 04:28:36 PM PDT 24 31640369 ps
T202 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1707501024 Aug 14 04:28:15 PM PDT 24 Aug 14 04:28:16 PM PDT 24 41691755 ps
T203 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2073492344 Aug 14 04:29:32 PM PDT 24 Aug 14 04:29:33 PM PDT 24 12631720 ps
T204 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.4291023942 Aug 14 04:28:44 PM PDT 24 Aug 14 04:28:45 PM PDT 24 44363697 ps
T205 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1281203627 Aug 14 04:28:40 PM PDT 24 Aug 14 04:28:40 PM PDT 24 12402475 ps

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.439859682
Short name T1
Test name
Test status
Simulation time 129071450 ps
CPU time 2.69 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 201340 kb
Host smart-fee2dee4-5b3b-41d1-82ac-c324a895897a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439859682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_tl_intg_err.439859682
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1307907349
Short name T16
Test name
Test status
Simulation time 137213151 ps
CPU time 2.77 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 209772 kb
Host smart-37e1920f-1938-44d1-9454-56970140053e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307907349 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1307907349
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1291510106
Short name T52
Test name
Test status
Simulation time 310825769 ps
CPU time 2.25 seconds
Started Aug 14 04:29:26 PM PDT 24
Finished Aug 14 04:29:29 PM PDT 24
Peak memory 217868 kb
Host smart-27328851-5655-49c4-becb-b0f16948e0ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291510106 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.1291510106
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3385920043
Short name T8
Test name
Test status
Simulation time 85016277 ps
CPU time 2.47 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:45 PM PDT 24
Peak memory 201332 kb
Host smart-120f6328-1496-4f7c-9a67-c9465b9f2858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385920043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.3385920043
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.2876865019
Short name T80
Test name
Test status
Simulation time 136000362 ps
CPU time 1.62 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:44 PM PDT 24
Peak memory 201352 kb
Host smart-da28efd4-cb29-4a4f-85c8-673233ab3033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876865019 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.2876865019
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.489697458
Short name T32
Test name
Test status
Simulation time 72769555 ps
CPU time 1.33 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 201332 kb
Host smart-b9f53af3-9708-42bf-b009-f419d1abc691
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489697458 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.clkmgr_shadow_reg_errors.489697458
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1205541770
Short name T134
Test name
Test status
Simulation time 50424636 ps
CPU time 1.84 seconds
Started Aug 14 04:28:50 PM PDT 24
Finished Aug 14 04:28:52 PM PDT 24
Peak memory 201328 kb
Host smart-525a23d5-af52-4ec0-a0ed-ac788ab6add7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205541770 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1205541770
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1561878484
Short name T47
Test name
Test status
Simulation time 784911734 ps
CPU time 4.03 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201296 kb
Host smart-d51224bb-9695-42ed-a994-ab415f7be963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561878484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1561878484
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1622304961
Short name T15
Test name
Test status
Simulation time 56331117 ps
CPU time 1.36 seconds
Started Aug 14 04:28:33 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201244 kb
Host smart-5f405dc9-8d83-4848-bfde-019bcd414304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622304961 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.1622304961
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.424587284
Short name T78
Test name
Test status
Simulation time 75551838 ps
CPU time 1.21 seconds
Started Aug 14 04:28:38 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 201060 kb
Host smart-8f9795d1-9259-4c12-94d0-09a5605ba17d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424587284 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.424587284
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3535321024
Short name T144
Test name
Test status
Simulation time 255294764 ps
CPU time 2.03 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 217900 kb
Host smart-5fc077ee-690a-4f32-957a-7e7c79f46c6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535321024 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3535321024
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1751127890
Short name T17
Test name
Test status
Simulation time 69371060 ps
CPU time 1.58 seconds
Started Aug 14 04:28:15 PM PDT 24
Finished Aug 14 04:28:17 PM PDT 24
Peak memory 201172 kb
Host smart-2aec1ce8-f3dc-43aa-810a-374ee20d1434
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751127890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.1751127890
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2879558168
Short name T159
Test name
Test status
Simulation time 56554777 ps
CPU time 1.29 seconds
Started Aug 14 04:28:39 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 201364 kb
Host smart-2a8d195a-f960-49c6-9ff6-c29db998c2b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879558168 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.2879558168
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1199458807
Short name T43
Test name
Test status
Simulation time 176557754 ps
CPU time 2.4 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201276 kb
Host smart-0e8a7f04-69a4-4ffc-a277-e9044acc9b69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199458807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.1199458807
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1784602442
Short name T39
Test name
Test status
Simulation time 97803998 ps
CPU time 2.29 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 201336 kb
Host smart-8d202193-cb0f-409c-a1e9-164cb512c92c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784602442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.1784602442
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2682291656
Short name T85
Test name
Test status
Simulation time 50790276 ps
CPU time 1.18 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 200872 kb
Host smart-8669ec8a-2a46-49c9-ad12-d8faf03b223e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682291656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.2682291656
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1274230318
Short name T26
Test name
Test status
Simulation time 352763245 ps
CPU time 4.01 seconds
Started Aug 14 04:29:04 PM PDT 24
Finished Aug 14 04:29:08 PM PDT 24
Peak memory 199720 kb
Host smart-f27aa301-089b-48da-bb03-0c5963c80fd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274230318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.1274230318
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1006802313
Short name T33
Test name
Test status
Simulation time 29151746 ps
CPU time 0.74 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 200968 kb
Host smart-7b342e21-c026-4036-80a6-1df16ae5dae6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006802313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.1006802313
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1869729148
Short name T10
Test name
Test status
Simulation time 180280010 ps
CPU time 1.45 seconds
Started Aug 14 04:29:40 PM PDT 24
Finished Aug 14 04:29:41 PM PDT 24
Peak memory 201132 kb
Host smart-10d97e73-2f40-4dd8-a88c-73686d4e4fac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869729148 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.1869729148
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1707501024
Short name T202
Test name
Test status
Simulation time 41691755 ps
CPU time 0.78 seconds
Started Aug 14 04:28:15 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 201028 kb
Host smart-9726fbcd-398d-4555-90eb-f2fc0add2845
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707501024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.1707501024
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.4000096012
Short name T191
Test name
Test status
Simulation time 14719479 ps
CPU time 0.7 seconds
Started Aug 14 04:28:29 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 199648 kb
Host smart-0e506a3c-2f25-4661-bf0a-c563b44cee7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000096012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.4000096012
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.698923459
Short name T165
Test name
Test status
Simulation time 48689440 ps
CPU time 1.34 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 201140 kb
Host smart-b956c55f-72b4-4338-8c98-9bc5d67a0382
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698923459 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.clkmgr_same_csr_outstanding.698923459
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.451286743
Short name T188
Test name
Test status
Simulation time 64888535 ps
CPU time 1.34 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 201348 kb
Host smart-6cf1c6c9-b6a2-4ede-8db8-7d979d1be00e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451286743 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.clkmgr_shadow_reg_errors.451286743
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.131977698
Short name T152
Test name
Test status
Simulation time 160129088 ps
CPU time 2.54 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 201756 kb
Host smart-19107f36-3776-4364-a63e-9a76c2941b2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131977698 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.131977698
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2648757618
Short name T194
Test name
Test status
Simulation time 61846498 ps
CPU time 1.84 seconds
Started Aug 14 04:28:41 PM PDT 24
Finished Aug 14 04:28:43 PM PDT 24
Peak memory 201260 kb
Host smart-bb6c7391-4b70-46e2-ad81-aea77d165e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648757618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.2648757618
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.587653121
Short name T35
Test name
Test status
Simulation time 59942263 ps
CPU time 1.67 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:32 PM PDT 24
Peak memory 201204 kb
Host smart-290d5e3c-f996-4c58-b620-36b9a33107b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587653121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_aliasing.587653121
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1223765310
Short name T37
Test name
Test status
Simulation time 1322725683 ps
CPU time 9.17 seconds
Started Aug 14 04:28:18 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 201276 kb
Host smart-ead725f0-cd6c-4316-a041-4f0ff36ddac6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223765310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.1223765310
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2691924478
Short name T176
Test name
Test status
Simulation time 16512007 ps
CPU time 0.76 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 200988 kb
Host smart-ab0b3bcb-b3b2-4c2e-8a0e-8d1865081494
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691924478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2691924478
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.8849456
Short name T45
Test name
Test status
Simulation time 45700327 ps
CPU time 1.4 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 201328 kb
Host smart-4250fea7-4511-44da-94df-a803392ee00c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8849456 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.8849456
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3855780276
Short name T6
Test name
Test status
Simulation time 59569155 ps
CPU time 0.92 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:29 PM PDT 24
Peak memory 201080 kb
Host smart-24b03148-c52b-4cf1-8a9f-4ec85bf37c2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855780276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.3855780276
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3373235802
Short name T121
Test name
Test status
Simulation time 31928944 ps
CPU time 0.67 seconds
Started Aug 14 04:28:19 PM PDT 24
Finished Aug 14 04:28:20 PM PDT 24
Peak memory 199652 kb
Host smart-0bc7d0d6-db17-4b04-b44e-01068b9ff999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373235802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.3373235802
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.4037122366
Short name T2
Test name
Test status
Simulation time 46443713 ps
CPU time 1 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 201136 kb
Host smart-89cd067d-b3e2-4d4b-a268-af4567dbc0ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037122366 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.4037122366
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2312891739
Short name T34
Test name
Test status
Simulation time 182246740 ps
CPU time 1.98 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 201488 kb
Host smart-211f9a59-c0b0-4985-913f-f055047f57ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312891739 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.2312891739
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.677774175
Short name T19
Test name
Test status
Simulation time 80704908 ps
CPU time 1.47 seconds
Started Aug 14 04:28:29 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 201268 kb
Host smart-9c1ac508-15c5-4a27-9517-4e11ef8b81ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677774175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkm
gr_tl_errors.677774175
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2327135125
Short name T46
Test name
Test status
Simulation time 425584353 ps
CPU time 3.28 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 201320 kb
Host smart-cd9ef7eb-5b35-4faa-9ed1-b2c879635113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327135125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.2327135125
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.1022449719
Short name T77
Test name
Test status
Simulation time 166563989 ps
CPU time 1.37 seconds
Started Aug 14 04:28:39 PM PDT 24
Finished Aug 14 04:28:41 PM PDT 24
Peak memory 201184 kb
Host smart-76e48180-7bee-406a-b0e7-3fcbef9860a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022449719 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.1022449719
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1414417684
Short name T151
Test name
Test status
Simulation time 22049912 ps
CPU time 0.85 seconds
Started Aug 14 04:28:50 PM PDT 24
Finished Aug 14 04:28:51 PM PDT 24
Peak memory 201068 kb
Host smart-9dc23c36-2a40-4377-b5a2-4d2e37775df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414417684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.1414417684
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.3268277387
Short name T135
Test name
Test status
Simulation time 20263975 ps
CPU time 0.7 seconds
Started Aug 14 04:28:38 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 199680 kb
Host smart-f2f5b87f-2c18-4970-95d0-62750de56fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268277387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.3268277387
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3088888148
Short name T140
Test name
Test status
Simulation time 118779886 ps
CPU time 2 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:45 PM PDT 24
Peak memory 209768 kb
Host smart-1d050d44-dfa9-4bf3-b28d-06f98c222249
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088888148 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.3088888148
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3120943491
Short name T5
Test name
Test status
Simulation time 86727475 ps
CPU time 1.81 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 209784 kb
Host smart-3dd12fb3-c14d-4df3-8a9b-1f29eaa307b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120943491 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3120943491
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2102994961
Short name T155
Test name
Test status
Simulation time 118713761 ps
CPU time 3.03 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:33 PM PDT 24
Peak memory 201276 kb
Host smart-ad374ad1-e29d-4f80-a964-737a5ef8f7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102994961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.2102994961
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3867881355
Short name T42
Test name
Test status
Simulation time 121076457 ps
CPU time 2.51 seconds
Started Aug 14 04:28:29 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201332 kb
Host smart-cd949253-d3c5-4ac5-b615-2bed8b77c47e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867881355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.3867881355
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.4224192143
Short name T183
Test name
Test status
Simulation time 20359108 ps
CPU time 0.85 seconds
Started Aug 14 04:28:29 PM PDT 24
Finished Aug 14 04:28:29 PM PDT 24
Peak memory 201016 kb
Host smart-f22c1669-3e58-4fe9-a91e-401ddb7cfc78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224192143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.4224192143
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2073492344
Short name T203
Test name
Test status
Simulation time 12631720 ps
CPU time 0.65 seconds
Started Aug 14 04:29:32 PM PDT 24
Finished Aug 14 04:29:33 PM PDT 24
Peak memory 199592 kb
Host smart-15c1a9d7-482b-4924-a171-22cf7931f8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073492344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.2073492344
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3170870520
Short name T168
Test name
Test status
Simulation time 59963723 ps
CPU time 1.33 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 201272 kb
Host smart-29078cb2-e321-4284-b668-d5e933e24a23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170870520 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.3170870520
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2295728395
Short name T64
Test name
Test status
Simulation time 495126636 ps
CPU time 2.98 seconds
Started Aug 14 04:28:31 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 209784 kb
Host smart-42cb7fa8-3764-4f0a-b2cd-3d85cf56638f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295728395 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.2295728395
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2435266799
Short name T61
Test name
Test status
Simulation time 170676692 ps
CPU time 2.61 seconds
Started Aug 14 04:28:56 PM PDT 24
Finished Aug 14 04:28:59 PM PDT 24
Peak memory 209820 kb
Host smart-f1770cc9-80a8-4741-89b5-9958e2c77dbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435266799 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.2435266799
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2097268705
Short name T172
Test name
Test status
Simulation time 304950511 ps
CPU time 2.98 seconds
Started Aug 14 04:28:54 PM PDT 24
Finished Aug 14 04:28:57 PM PDT 24
Peak memory 201304 kb
Host smart-31bed2ca-7f79-4330-a6e7-59479b7298c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097268705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.2097268705
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.552590848
Short name T179
Test name
Test status
Simulation time 53799442 ps
CPU time 1.59 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201288 kb
Host smart-1eebdd8a-c613-405c-bb49-f820c0bb940d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552590848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.clkmgr_tl_intg_err.552590848
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.4162864885
Short name T173
Test name
Test status
Simulation time 69015872 ps
CPU time 1.26 seconds
Started Aug 14 04:28:36 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201192 kb
Host smart-6dbd89f3-4bab-450f-8315-3ff93c62da01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162864885 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.4162864885
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2550802585
Short name T93
Test name
Test status
Simulation time 17629961 ps
CPU time 0.78 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:41 PM PDT 24
Peak memory 201032 kb
Host smart-d0d41b99-be7b-4c6d-8bb3-51c3597b91c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550802585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.2550802585
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.4071422023
Short name T158
Test name
Test status
Simulation time 28702142 ps
CPU time 0.73 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:23 PM PDT 24
Peak memory 199700 kb
Host smart-395d5c39-5275-4a53-aeba-e3badc7d5b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071422023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.4071422023
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3752330515
Short name T95
Test name
Test status
Simulation time 298028263 ps
CPU time 1.56 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 201120 kb
Host smart-26bb083c-8465-4721-ad7c-c08bf962f638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752330515 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.3752330515
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3777360759
Short name T53
Test name
Test status
Simulation time 225345618 ps
CPU time 1.87 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 201540 kb
Host smart-117e3e0a-a36c-410a-b84a-7067aceee8b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777360759 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.3777360759
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1803302326
Short name T161
Test name
Test status
Simulation time 166268162 ps
CPU time 2.87 seconds
Started Aug 14 04:28:43 PM PDT 24
Finished Aug 14 04:28:46 PM PDT 24
Peak memory 201268 kb
Host smart-326c9bcf-9245-418e-993e-848fc0118d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803302326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.1803302326
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.3355189659
Short name T48
Test name
Test status
Simulation time 97765171 ps
CPU time 2.25 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201340 kb
Host smart-062cf01d-6393-4497-8af1-61454688cbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355189659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.3355189659
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2792256198
Short name T79
Test name
Test status
Simulation time 39621656 ps
CPU time 1.2 seconds
Started Aug 14 04:28:54 PM PDT 24
Finished Aug 14 04:28:55 PM PDT 24
Peak memory 201192 kb
Host smart-abf298e1-305d-45f7-923c-bf53f1d468ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792256198 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.2792256198
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.799516332
Short name T200
Test name
Test status
Simulation time 46798982 ps
CPU time 0.83 seconds
Started Aug 14 04:29:36 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 200864 kb
Host smart-f2f27bdd-9511-4b62-988a-577106af462a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799516332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
clkmgr_csr_rw.799516332
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2122034450
Short name T190
Test name
Test status
Simulation time 36978905 ps
CPU time 0.72 seconds
Started Aug 14 04:28:36 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 199592 kb
Host smart-b9061d13-1a3e-4389-b3e1-456b7767b7d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122034450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.2122034450
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2743662727
Short name T167
Test name
Test status
Simulation time 78652553 ps
CPU time 1.31 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201300 kb
Host smart-d218aa16-315c-4eca-9835-6a33945dab22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743662727 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.2743662727
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1740849097
Short name T56
Test name
Test status
Simulation time 151518780 ps
CPU time 2.73 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 209684 kb
Host smart-67a9ee6f-4026-4797-9dfb-2a2cacf79ce8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740849097 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1740849097
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2470797147
Short name T103
Test name
Test status
Simulation time 184348122 ps
CPU time 2.96 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 201312 kb
Host smart-d37cbfdf-2296-4f1d-83d4-e7d048f4ce32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470797147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.2470797147
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.527978457
Short name T49
Test name
Test status
Simulation time 135236117 ps
CPU time 2.72 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 201248 kb
Host smart-ad2ece28-f488-4f1c-8d50-5020c1c74104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527978457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.clkmgr_tl_intg_err.527978457
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1994429444
Short name T154
Test name
Test status
Simulation time 302707486 ps
CPU time 1.77 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:35 PM PDT 24
Peak memory 201188 kb
Host smart-42a378d4-0245-4181-8012-5bd385af7eff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994429444 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.1994429444
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2855877862
Short name T114
Test name
Test status
Simulation time 17824456 ps
CPU time 0.82 seconds
Started Aug 14 04:28:41 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 201068 kb
Host smart-ef3250d3-1cb3-47cc-9331-aa3d1d5f7ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855877862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.2855877862
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1216120262
Short name T58
Test name
Test status
Simulation time 119990091 ps
CPU time 0.95 seconds
Started Aug 14 04:28:47 PM PDT 24
Finished Aug 14 04:28:48 PM PDT 24
Peak memory 199712 kb
Host smart-7138c7ac-6397-452c-a0ea-cbcea3e229c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216120262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.1216120262
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2536717725
Short name T13
Test name
Test status
Simulation time 106922916 ps
CPU time 1.3 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:43 PM PDT 24
Peak memory 201232 kb
Host smart-7604e6a0-9695-404f-a444-34559c71f650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536717725 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.2536717725
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.620475304
Short name T24
Test name
Test status
Simulation time 98716004 ps
CPU time 1.89 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 209760 kb
Host smart-d8ee70c9-ccf6-4037-a8bc-bca29d9d1502
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620475304 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.620475304
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.437987659
Short name T153
Test name
Test status
Simulation time 65683708 ps
CPU time 1.65 seconds
Started Aug 14 04:28:47 PM PDT 24
Finished Aug 14 04:28:49 PM PDT 24
Peak memory 201264 kb
Host smart-41631479-18b4-4327-86d9-b6fc21c09d41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437987659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk
mgr_tl_errors.437987659
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.463336265
Short name T83
Test name
Test status
Simulation time 39484975 ps
CPU time 1.86 seconds
Started Aug 14 04:28:41 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 217728 kb
Host smart-ae7b5e01-cd15-4f20-a23b-8492180a7b1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463336265 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.463336265
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4220451108
Short name T196
Test name
Test status
Simulation time 16926810 ps
CPU time 0.74 seconds
Started Aug 14 04:28:36 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201048 kb
Host smart-6a6c482e-f8cd-4df8-838a-6f51e0c2131b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220451108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.4220451108
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2570348370
Short name T87
Test name
Test status
Simulation time 17090366 ps
CPU time 0.68 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 199620 kb
Host smart-e1b21c0b-eba2-47f9-804c-26477470b00d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570348370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2570348370
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3445384516
Short name T119
Test name
Test status
Simulation time 24817881 ps
CPU time 0.96 seconds
Started Aug 14 04:28:36 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201120 kb
Host smart-8d6bc767-b267-4e2f-a881-965c7ba0fcdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445384516 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.3445384516
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3647895292
Short name T118
Test name
Test status
Simulation time 66565215 ps
CPU time 1.44 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:41 PM PDT 24
Peak memory 201216 kb
Host smart-afa35213-84a1-4e33-b31d-bfc4cac20a5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647895292 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3647895292
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3329491142
Short name T9
Test name
Test status
Simulation time 15686735 ps
CPU time 0.73 seconds
Started Aug 14 04:28:50 PM PDT 24
Finished Aug 14 04:28:51 PM PDT 24
Peak memory 200968 kb
Host smart-4b6d02c3-6c18-483c-8249-a48cc3e67507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329491142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.3329491142
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2821632665
Short name T101
Test name
Test status
Simulation time 26713675 ps
CPU time 0.66 seconds
Started Aug 14 04:28:31 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 199624 kb
Host smart-abfe1255-2b76-4fde-b36a-acb3c8ae2dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821632665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.2821632665
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3517096482
Short name T169
Test name
Test status
Simulation time 152264909 ps
CPU time 1.66 seconds
Started Aug 14 04:28:45 PM PDT 24
Finished Aug 14 04:28:47 PM PDT 24
Peak memory 201356 kb
Host smart-3ed035dd-3ad0-4e67-a507-97adfda63877
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517096482 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.3517096482
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3403682010
Short name T62
Test name
Test status
Simulation time 186212233 ps
CPU time 1.62 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:44 PM PDT 24
Peak memory 201360 kb
Host smart-1b10654b-bad4-4a18-abbd-67890dda5f1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403682010 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.3403682010
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3066855718
Short name T65
Test name
Test status
Simulation time 667209404 ps
CPU time 3.64 seconds
Started Aug 14 04:29:31 PM PDT 24
Finished Aug 14 04:29:34 PM PDT 24
Peak memory 201792 kb
Host smart-a126e39f-22ef-4f29-aa00-27436c347827
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066855718 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.3066855718
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2263475361
Short name T30
Test name
Test status
Simulation time 64498715 ps
CPU time 1.97 seconds
Started Aug 14 04:28:57 PM PDT 24
Finished Aug 14 04:28:59 PM PDT 24
Peak memory 201344 kb
Host smart-6418b51c-0127-477f-a497-3cbabcaedde0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263475361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.2263475361
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.985069252
Short name T22
Test name
Test status
Simulation time 138178499 ps
CPU time 2.68 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:43 PM PDT 24
Peak memory 201248 kb
Host smart-9894380a-811e-46af-b002-6de34b1519f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985069252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.clkmgr_tl_intg_err.985069252
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.795332994
Short name T187
Test name
Test status
Simulation time 54375965 ps
CPU time 1.09 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201080 kb
Host smart-23afb08a-824b-4bb0-a9b6-ebc18b4c7cb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795332994 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.795332994
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2931571567
Short name T126
Test name
Test status
Simulation time 97995360 ps
CPU time 1.03 seconds
Started Aug 14 04:28:36 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 201296 kb
Host smart-002fa8f6-75ef-44fd-9374-6a2064a5a041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931571567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.2931571567
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2927182484
Short name T90
Test name
Test status
Simulation time 34237814 ps
CPU time 0.69 seconds
Started Aug 14 04:28:44 PM PDT 24
Finished Aug 14 04:28:44 PM PDT 24
Peak memory 199680 kb
Host smart-eda048a9-c0bb-4630-a781-b5519f041139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927182484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.2927182484
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1052117283
Short name T71
Test name
Test status
Simulation time 41006523 ps
CPU time 1.09 seconds
Started Aug 14 04:29:08 PM PDT 24
Finished Aug 14 04:29:09 PM PDT 24
Peak memory 201124 kb
Host smart-57175742-29a6-4139-8339-318cc3ad79e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052117283 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.1052117283
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1420267158
Short name T122
Test name
Test status
Simulation time 79306329 ps
CPU time 1.18 seconds
Started Aug 14 04:28:50 PM PDT 24
Finished Aug 14 04:28:52 PM PDT 24
Peak memory 201336 kb
Host smart-88c892b5-6f52-4748-a437-e1f52555e1a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420267158 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.1420267158
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.882011293
Short name T125
Test name
Test status
Simulation time 299480634 ps
CPU time 2.38 seconds
Started Aug 14 04:28:36 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 209732 kb
Host smart-f137300f-5974-4520-a323-4850c6f1ee38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882011293 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.882011293
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2087821937
Short name T130
Test name
Test status
Simulation time 23252864 ps
CPU time 1.38 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201272 kb
Host smart-86732c19-7f33-4267-9ee6-447141f6b0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087821937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.2087821937
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1095249603
Short name T146
Test name
Test status
Simulation time 329858588 ps
CPU time 3.01 seconds
Started Aug 14 04:29:05 PM PDT 24
Finished Aug 14 04:29:08 PM PDT 24
Peak memory 201308 kb
Host smart-afe8b7c0-8429-495b-915c-778546bf27e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095249603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.1095249603
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3644714727
Short name T4
Test name
Test status
Simulation time 33303258 ps
CPU time 0.96 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:44 PM PDT 24
Peak memory 201188 kb
Host smart-51f3a08e-263a-44c9-8387-844d9275aebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644714727 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.3644714727
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.514060217
Short name T177
Test name
Test status
Simulation time 15227939 ps
CPU time 0.75 seconds
Started Aug 14 04:28:53 PM PDT 24
Finished Aug 14 04:28:54 PM PDT 24
Peak memory 200872 kb
Host smart-fa1a26da-ca99-4760-9c56-737dbea15bfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514060217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
clkmgr_csr_rw.514060217
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.945768198
Short name T84
Test name
Test status
Simulation time 16252810 ps
CPU time 0.66 seconds
Started Aug 14 04:28:54 PM PDT 24
Finished Aug 14 04:28:55 PM PDT 24
Peak memory 199648 kb
Host smart-82777f4d-0777-47c3-b485-fd935928e8c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945768198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_intr_test.945768198
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.288118828
Short name T36
Test name
Test status
Simulation time 27280478 ps
CPU time 0.87 seconds
Started Aug 14 04:28:43 PM PDT 24
Finished Aug 14 04:28:44 PM PDT 24
Peak memory 201048 kb
Host smart-d089bbb5-fdef-4722-bb9a-35075d5d7331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288118828 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 18.clkmgr_same_csr_outstanding.288118828
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2275332432
Short name T55
Test name
Test status
Simulation time 160743741 ps
CPU time 1.9 seconds
Started Aug 14 04:29:07 PM PDT 24
Finished Aug 14 04:29:09 PM PDT 24
Peak memory 201640 kb
Host smart-aaa6c16a-6c67-425e-a0ba-9064008ca7ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275332432 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.2275332432
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2095119893
Short name T166
Test name
Test status
Simulation time 129419136 ps
CPU time 1.59 seconds
Started Aug 14 04:28:33 PM PDT 24
Finished Aug 14 04:28:35 PM PDT 24
Peak memory 209720 kb
Host smart-3c5732d0-df6a-42b2-85b1-fd4317b5ce34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095119893 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.2095119893
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.895798287
Short name T162
Test name
Test status
Simulation time 259776529 ps
CPU time 3.47 seconds
Started Aug 14 04:28:41 PM PDT 24
Finished Aug 14 04:28:45 PM PDT 24
Peak memory 201272 kb
Host smart-57016fe0-dfdb-404f-9b19-ccbbfc28547d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895798287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_tl_errors.895798287
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3383539930
Short name T20
Test name
Test status
Simulation time 384515929 ps
CPU time 3.29 seconds
Started Aug 14 04:28:46 PM PDT 24
Finished Aug 14 04:28:50 PM PDT 24
Peak memory 201292 kb
Host smart-d42df607-e75d-4a2f-9c33-c7fcafddc667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383539930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.3383539930
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3020832489
Short name T192
Test name
Test status
Simulation time 305612329 ps
CPU time 1.86 seconds
Started Aug 14 04:28:50 PM PDT 24
Finished Aug 14 04:28:53 PM PDT 24
Peak memory 201196 kb
Host smart-5eb795d7-74aa-49b7-8e32-9163c2446407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020832489 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3020832489
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1705511728
Short name T124
Test name
Test status
Simulation time 45277476 ps
CPU time 0.79 seconds
Started Aug 14 04:28:38 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 200972 kb
Host smart-2cf72446-5bfb-4cbe-a08c-dabe5e6ab1b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705511728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.1705511728
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2519789988
Short name T91
Test name
Test status
Simulation time 18278188 ps
CPU time 0.71 seconds
Started Aug 14 04:28:36 PM PDT 24
Finished Aug 14 04:28:37 PM PDT 24
Peak memory 199616 kb
Host smart-b04dbc3e-626c-4658-99a9-a9db93797942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519789988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2519789988
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1416926579
Short name T143
Test name
Test status
Simulation time 196447090 ps
CPU time 1.48 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:43 PM PDT 24
Peak memory 201284 kb
Host smart-78d8fc42-3e0f-47d4-9b2f-821be3fc166d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416926579 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.1416926579
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3161052057
Short name T50
Test name
Test status
Simulation time 87887420 ps
CPU time 1.43 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 201364 kb
Host smart-bdff5f82-04ff-4742-924a-a592c6b196ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161052057 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.3161052057
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1430657800
Short name T59
Test name
Test status
Simulation time 228016928 ps
CPU time 2.17 seconds
Started Aug 14 04:28:58 PM PDT 24
Finished Aug 14 04:29:00 PM PDT 24
Peak memory 209784 kb
Host smart-2ad1b62b-b2bd-443e-adbf-6c7cae39ef32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430657800 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.1430657800
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.4291023942
Short name T204
Test name
Test status
Simulation time 44363697 ps
CPU time 1.45 seconds
Started Aug 14 04:28:44 PM PDT 24
Finished Aug 14 04:28:45 PM PDT 24
Peak memory 201240 kb
Host smart-621cf6be-edea-43a6-9d43-e5698ebc01a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291023942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.4291023942
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2665718381
Short name T82
Test name
Test status
Simulation time 98458614 ps
CPU time 2.24 seconds
Started Aug 14 04:28:39 PM PDT 24
Finished Aug 14 04:28:41 PM PDT 24
Peak memory 201300 kb
Host smart-827a840a-26d1-45d8-a2bd-6f1358ec390d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665718381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.2665718381
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1287688242
Short name T178
Test name
Test status
Simulation time 92556823 ps
CPU time 1.61 seconds
Started Aug 14 04:28:15 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 201264 kb
Host smart-eea9c277-7999-4f10-b319-c9922fd56f43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287688242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.1287688242
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.216844871
Short name T75
Test name
Test status
Simulation time 1908296935 ps
CPU time 11.02 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:46 PM PDT 24
Peak memory 201128 kb
Host smart-56508ab5-1e89-42ae-9bca-2c3dcbf8266e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216844871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_bit_bash.216844871
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1956308288
Short name T76
Test name
Test status
Simulation time 22586803 ps
CPU time 1 seconds
Started Aug 14 04:28:38 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 201056 kb
Host smart-6216c201-d228-4095-b549-b5cc7c28019a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956308288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.1956308288
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2854321868
Short name T18
Test name
Test status
Simulation time 19206750 ps
CPU time 1.02 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 201128 kb
Host smart-b125f1e7-f654-4604-bba0-23d656a588c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854321868 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.2854321868
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.724946414
Short name T92
Test name
Test status
Simulation time 70983993 ps
CPU time 0.93 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 201020 kb
Host smart-7181c29d-e7b4-410c-8f91-917d2ee84f43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724946414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.c
lkmgr_csr_rw.724946414
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.1357555644
Short name T150
Test name
Test status
Simulation time 14284155 ps
CPU time 0.7 seconds
Started Aug 14 04:28:18 PM PDT 24
Finished Aug 14 04:28:19 PM PDT 24
Peak memory 199696 kb
Host smart-ac76e059-452e-4b0f-a45b-2e8cc8f5109f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357555644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.1357555644
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1164772816
Short name T120
Test name
Test status
Simulation time 96291109 ps
CPU time 1.5 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 201340 kb
Host smart-1a95b3de-58e2-44a6-be79-645481fb7ab5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164772816 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.1164772816
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2019678561
Short name T54
Test name
Test status
Simulation time 63323230 ps
CPU time 1.24 seconds
Started Aug 14 04:28:21 PM PDT 24
Finished Aug 14 04:28:22 PM PDT 24
Peak memory 201388 kb
Host smart-2021a2bb-0efd-4876-b938-3a240e4a0aa9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019678561 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.2019678561
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3138829702
Short name T68
Test name
Test status
Simulation time 54204182 ps
CPU time 1.54 seconds
Started Aug 14 04:28:29 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 209744 kb
Host smart-77497881-e04e-45c3-9f1f-a7613fcbe237
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138829702 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.3138829702
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.12934459
Short name T184
Test name
Test status
Simulation time 73912138 ps
CPU time 2.27 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 201264 kb
Host smart-2c54e4a1-38de-410a-83bd-aa4fa66f10ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmg
r_tl_errors.12934459
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.66081907
Short name T40
Test name
Test status
Simulation time 914468376 ps
CPU time 4.59 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 201352 kb
Host smart-e4f9eaaf-0562-4cf7-8e02-d47ecadb997e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66081907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.clkmgr_tl_intg_err.66081907
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2390999827
Short name T107
Test name
Test status
Simulation time 11851609 ps
CPU time 0.69 seconds
Started Aug 14 04:29:13 PM PDT 24
Finished Aug 14 04:29:13 PM PDT 24
Peak memory 199592 kb
Host smart-1539cc67-6440-4c5a-a98b-a6671950c500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390999827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.2390999827
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3068638955
Short name T127
Test name
Test status
Simulation time 33255092 ps
CPU time 0.67 seconds
Started Aug 14 04:28:45 PM PDT 24
Finished Aug 14 04:28:46 PM PDT 24
Peak memory 199632 kb
Host smart-77d24b49-56c2-44d0-aaa4-71e37848ab52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068638955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.3068638955
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3829938406
Short name T117
Test name
Test status
Simulation time 13565597 ps
CPU time 0.66 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 199576 kb
Host smart-f3e68f27-db56-44f0-a19c-ff4e929cca51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829938406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.3829938406
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.716314643
Short name T112
Test name
Test status
Simulation time 21152578 ps
CPU time 0.67 seconds
Started Aug 14 04:28:50 PM PDT 24
Finished Aug 14 04:28:50 PM PDT 24
Peak memory 199572 kb
Host smart-bf569ad9-3e64-49f7-acf9-0dbc667ab2e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716314643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clk
mgr_intr_test.716314643
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3867493852
Short name T104
Test name
Test status
Simulation time 37829098 ps
CPU time 0.75 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:43 PM PDT 24
Peak memory 199680 kb
Host smart-cd657461-11dc-4cba-b2ca-8dda62c5d60a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867493852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.3867493852
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.1747267126
Short name T129
Test name
Test status
Simulation time 27700867 ps
CPU time 0.69 seconds
Started Aug 14 04:29:13 PM PDT 24
Finished Aug 14 04:29:14 PM PDT 24
Peak memory 199612 kb
Host smart-240973dd-85b5-40eb-9a74-8a0899aa5366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747267126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.1747267126
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1322757506
Short name T174
Test name
Test status
Simulation time 31920661 ps
CPU time 0.69 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:35 PM PDT 24
Peak memory 199652 kb
Host smart-b6a803e4-0de6-4f16-a899-a63bb51840b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322757506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.1322757506
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3924848601
Short name T157
Test name
Test status
Simulation time 15181387 ps
CPU time 0.68 seconds
Started Aug 14 04:28:41 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 199632 kb
Host smart-38d0a9bb-686c-4115-9e7f-ede51031aa27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924848601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.3924848601
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.282252023
Short name T102
Test name
Test status
Simulation time 13816269 ps
CPU time 0.68 seconds
Started Aug 14 04:28:38 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 199612 kb
Host smart-3fc08b4f-5fa4-4b07-b75e-b809fb608e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282252023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk
mgr_intr_test.282252023
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.4201820677
Short name T94
Test name
Test status
Simulation time 37097895 ps
CPU time 0.7 seconds
Started Aug 14 04:28:57 PM PDT 24
Finished Aug 14 04:28:58 PM PDT 24
Peak memory 199572 kb
Host smart-9f19f4c3-b4bf-4266-9c37-ab3d5a588cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201820677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.4201820677
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3779725906
Short name T137
Test name
Test status
Simulation time 130596349 ps
CPU time 1.49 seconds
Started Aug 14 04:28:20 PM PDT 24
Finished Aug 14 04:28:22 PM PDT 24
Peak memory 201108 kb
Host smart-57485324-5586-4553-b2ff-779c249c1d96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779725906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.3779725906
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2232653743
Short name T198
Test name
Test status
Simulation time 845166823 ps
CPU time 7.3 seconds
Started Aug 14 04:29:40 PM PDT 24
Finished Aug 14 04:29:48 PM PDT 24
Peak memory 201148 kb
Host smart-2fe59a5d-1343-47b0-a142-3eef36af1951
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232653743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.2232653743
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2130900160
Short name T74
Test name
Test status
Simulation time 68261079 ps
CPU time 0.96 seconds
Started Aug 14 04:28:38 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 201084 kb
Host smart-6a33e143-a438-432b-8a4a-528a4f29218c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130900160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.2130900160
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.687533297
Short name T11
Test name
Test status
Simulation time 38176859 ps
CPU time 1.21 seconds
Started Aug 14 04:29:30 PM PDT 24
Finished Aug 14 04:29:31 PM PDT 24
Peak memory 201132 kb
Host smart-edcd52a1-b2e3-40a5-934c-355009c704b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687533297 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.687533297
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2329712359
Short name T97
Test name
Test status
Simulation time 42909794 ps
CPU time 0.86 seconds
Started Aug 14 04:28:22 PM PDT 24
Finished Aug 14 04:28:22 PM PDT 24
Peak memory 201032 kb
Host smart-552c3a3f-7903-47e8-b694-aca30df9a7dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329712359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.2329712359
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.374761157
Short name T106
Test name
Test status
Simulation time 30700608 ps
CPU time 0.71 seconds
Started Aug 14 04:28:17 PM PDT 24
Finished Aug 14 04:28:18 PM PDT 24
Peak memory 199652 kb
Host smart-8c013e3a-129f-408a-8137-7d471169017c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374761157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm
gr_intr_test.374761157
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.20135537
Short name T14
Test name
Test status
Simulation time 51663885 ps
CPU time 1.24 seconds
Started Aug 14 04:29:32 PM PDT 24
Finished Aug 14 04:29:39 PM PDT 24
Peak memory 201048 kb
Host smart-f855651b-6a9d-46aa-b485-75f3b1ce9e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20135537 -assert nopostproc +UVM_TESTNAME=clkmgr_ba
se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.clkmgr_same_csr_outstanding.20135537
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2094220507
Short name T171
Test name
Test status
Simulation time 68500461 ps
CPU time 1.3 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:25 PM PDT 24
Peak memory 201348 kb
Host smart-2373f22c-e622-42a0-ba37-b8624b1cb2cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094220507 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.2094220507
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4124466307
Short name T189
Test name
Test status
Simulation time 142271320 ps
CPU time 2.33 seconds
Started Aug 14 04:28:20 PM PDT 24
Finished Aug 14 04:28:22 PM PDT 24
Peak memory 201592 kb
Host smart-8d89ae1d-a8af-4b6c-ad07-ba79960c1a8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124466307 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.4124466307
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2224888333
Short name T108
Test name
Test status
Simulation time 44534294 ps
CPU time 1.45 seconds
Started Aug 14 04:28:29 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 201260 kb
Host smart-6d1aa81f-c302-4f54-b13d-7b1ea6d40730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224888333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2224888333
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.88851607
Short name T163
Test name
Test status
Simulation time 114302851 ps
CPU time 1.71 seconds
Started Aug 14 04:28:16 PM PDT 24
Finished Aug 14 04:28:18 PM PDT 24
Peak memory 201200 kb
Host smart-652e4b19-9c5d-40f5-a7b6-3906fd9a62a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88851607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.clkmgr_tl_intg_err.88851607
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2371950720
Short name T132
Test name
Test status
Simulation time 27261078 ps
CPU time 0.69 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 199564 kb
Host smart-6543bdbb-8c0c-4817-8044-625f9e50aeab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371950720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.2371950720
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3589701149
Short name T138
Test name
Test status
Simulation time 94204118 ps
CPU time 0.81 seconds
Started Aug 14 04:28:43 PM PDT 24
Finished Aug 14 04:28:44 PM PDT 24
Peak memory 199636 kb
Host smart-3ea281bc-fa28-40b6-893b-dca02be3d083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589701149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.3589701149
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1092593494
Short name T139
Test name
Test status
Simulation time 22285887 ps
CPU time 0.68 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:43 PM PDT 24
Peak memory 199616 kb
Host smart-55892aaf-2eed-44e8-8bad-9236ceb5c867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092593494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.1092593494
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2182100245
Short name T72
Test name
Test status
Simulation time 32129095 ps
CPU time 0.67 seconds
Started Aug 14 04:28:56 PM PDT 24
Finished Aug 14 04:28:57 PM PDT 24
Peak memory 199716 kb
Host smart-14b62b26-15e9-4e65-87cf-016637d69822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182100245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.2182100245
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.297070107
Short name T185
Test name
Test status
Simulation time 13113705 ps
CPU time 0.62 seconds
Started Aug 14 04:28:39 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 199600 kb
Host smart-5ca210dd-6369-43b2-9797-f9141122e016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297070107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk
mgr_intr_test.297070107
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1304388579
Short name T180
Test name
Test status
Simulation time 40831810 ps
CPU time 0.71 seconds
Started Aug 14 04:28:55 PM PDT 24
Finished Aug 14 04:28:55 PM PDT 24
Peak memory 199648 kb
Host smart-354f3542-435d-4095-88e6-8538e432e4c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304388579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.1304388579
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1273260715
Short name T113
Test name
Test status
Simulation time 12392752 ps
CPU time 0.65 seconds
Started Aug 14 04:28:50 PM PDT 24
Finished Aug 14 04:28:51 PM PDT 24
Peak memory 199712 kb
Host smart-64fb77e2-510b-4a23-b2da-c8db5b8c7d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273260715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.1273260715
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3232151289
Short name T193
Test name
Test status
Simulation time 13044033 ps
CPU time 0.67 seconds
Started Aug 14 04:28:38 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 199584 kb
Host smart-15352bd0-c5c7-41c1-83b1-449a6f2f4e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232151289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.3232151289
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.817730767
Short name T73
Test name
Test status
Simulation time 13740419 ps
CPU time 0.66 seconds
Started Aug 14 04:29:02 PM PDT 24
Finished Aug 14 04:29:03 PM PDT 24
Peak memory 199648 kb
Host smart-8ce9df5f-19e7-4d6e-a0d1-1a58fb285f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817730767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clk
mgr_intr_test.817730767
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.724604308
Short name T141
Test name
Test status
Simulation time 13095157 ps
CPU time 0.66 seconds
Started Aug 14 04:29:02 PM PDT 24
Finished Aug 14 04:29:03 PM PDT 24
Peak memory 199628 kb
Host smart-d5793e64-c04d-4578-9708-f708c4a7478d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724604308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clk
mgr_intr_test.724604308
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2931987127
Short name T86
Test name
Test status
Simulation time 33336486 ps
CPU time 1.18 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 201056 kb
Host smart-213e1cd5-7c5a-49cf-88b0-23e6231c4b87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931987127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.2931987127
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1078588207
Short name T27
Test name
Test status
Simulation time 209119317 ps
CPU time 3.68 seconds
Started Aug 14 04:28:17 PM PDT 24
Finished Aug 14 04:28:20 PM PDT 24
Peak memory 201160 kb
Host smart-db800dad-4ca8-440f-b704-b725724839c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078588207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.1078588207
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.445503074
Short name T98
Test name
Test status
Simulation time 47546244 ps
CPU time 0.78 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 200848 kb
Host smart-4a9065aa-4455-42cd-b2aa-2d8421a13329
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445503074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_hw_reset.445503074
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2689361382
Short name T199
Test name
Test status
Simulation time 24321416 ps
CPU time 0.94 seconds
Started Aug 14 04:28:46 PM PDT 24
Finished Aug 14 04:28:47 PM PDT 24
Peak memory 201180 kb
Host smart-50bf1690-5fe3-4e82-82d2-25fce3ef154f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689361382 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.2689361382
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1534734052
Short name T99
Test name
Test status
Simulation time 14346677 ps
CPU time 0.74 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 200908 kb
Host smart-6ddfed0b-45d0-4642-8765-e092ee9de793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534734052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.1534734052
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1750672672
Short name T160
Test name
Test status
Simulation time 30063376 ps
CPU time 0.71 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:41 PM PDT 24
Peak memory 199656 kb
Host smart-00ffffde-fa1e-4a28-b228-5b4cae0a09fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750672672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.1750672672
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2186857311
Short name T128
Test name
Test status
Simulation time 97534861 ps
CPU time 1.09 seconds
Started Aug 14 04:28:39 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 201140 kb
Host smart-312ce4b1-ea0a-4905-9bd7-94e80717615f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186857311 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.2186857311
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3615946768
Short name T70
Test name
Test status
Simulation time 193706679 ps
CPU time 2.34 seconds
Started Aug 14 04:29:04 PM PDT 24
Finished Aug 14 04:29:07 PM PDT 24
Peak memory 208272 kb
Host smart-12cea4c2-8af4-475d-b9f9-95bdd082a44c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615946768 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.3615946768
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.4071068132
Short name T116
Test name
Test status
Simulation time 132747871 ps
CPU time 2.74 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 209804 kb
Host smart-e4b7e19d-e229-474d-b68e-be830bcdb9bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071068132 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.4071068132
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1425030782
Short name T186
Test name
Test status
Simulation time 142167691 ps
CPU time 2.47 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:25 PM PDT 24
Peak memory 201248 kb
Host smart-a8733dba-7cbf-4301-ab76-896a8df95158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425030782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.1425030782
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3166059049
Short name T3
Test name
Test status
Simulation time 58527040 ps
CPU time 0.76 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:35 PM PDT 24
Peak memory 199640 kb
Host smart-2369e4e7-a075-4046-b25c-0a874d1c5ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166059049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.3166059049
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2283867952
Short name T109
Test name
Test status
Simulation time 11840616 ps
CPU time 0.66 seconds
Started Aug 14 04:28:45 PM PDT 24
Finished Aug 14 04:28:46 PM PDT 24
Peak memory 199648 kb
Host smart-808aa820-9538-433f-83ec-f352718e8260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283867952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2283867952
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.669586157
Short name T88
Test name
Test status
Simulation time 25321968 ps
CPU time 0.72 seconds
Started Aug 14 04:29:04 PM PDT 24
Finished Aug 14 04:29:05 PM PDT 24
Peak memory 199580 kb
Host smart-e67ca6d4-2fe7-48e2-98b4-531959ffac55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669586157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clk
mgr_intr_test.669586157
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1976361867
Short name T89
Test name
Test status
Simulation time 18708837 ps
CPU time 0.7 seconds
Started Aug 14 04:28:55 PM PDT 24
Finished Aug 14 04:28:56 PM PDT 24
Peak memory 199712 kb
Host smart-4c3f953d-5420-4319-991a-b2b5174b1af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976361867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.1976361867
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.341244214
Short name T123
Test name
Test status
Simulation time 11285278 ps
CPU time 0.64 seconds
Started Aug 14 04:29:03 PM PDT 24
Finished Aug 14 04:29:04 PM PDT 24
Peak memory 199656 kb
Host smart-beafe15f-a28c-4e98-ace5-67bbaabad9d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341244214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clk
mgr_intr_test.341244214
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4001865884
Short name T195
Test name
Test status
Simulation time 26395005 ps
CPU time 0.68 seconds
Started Aug 14 04:29:20 PM PDT 24
Finished Aug 14 04:29:21 PM PDT 24
Peak memory 199620 kb
Host smart-5366c178-c5ec-4205-b90d-02675093b265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001865884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.4001865884
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2525733017
Short name T96
Test name
Test status
Simulation time 15587442 ps
CPU time 0.62 seconds
Started Aug 14 04:28:54 PM PDT 24
Finished Aug 14 04:28:55 PM PDT 24
Peak memory 199624 kb
Host smart-e943c192-58e1-4f9e-8cee-fd17c4464ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525733017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.2525733017
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.280244620
Short name T170
Test name
Test status
Simulation time 77693512 ps
CPU time 0.8 seconds
Started Aug 14 04:29:10 PM PDT 24
Finished Aug 14 04:29:11 PM PDT 24
Peak memory 199512 kb
Host smart-dd646fd5-b1a2-4809-9ce1-7ffc21449d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280244620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clk
mgr_intr_test.280244620
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1905681881
Short name T100
Test name
Test status
Simulation time 33772796 ps
CPU time 0.7 seconds
Started Aug 14 04:29:14 PM PDT 24
Finished Aug 14 04:29:15 PM PDT 24
Peak memory 199676 kb
Host smart-17f13b7d-ac15-40ab-a613-fc47421cf175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905681881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.1905681881
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2141469548
Short name T175
Test name
Test status
Simulation time 38783198 ps
CPU time 0.75 seconds
Started Aug 14 04:28:56 PM PDT 24
Finished Aug 14 04:28:57 PM PDT 24
Peak memory 199876 kb
Host smart-cfb73330-60c3-4626-a6b8-29644cc0988d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141469548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.2141469548
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1144326306
Short name T164
Test name
Test status
Simulation time 48354171 ps
CPU time 0.81 seconds
Started Aug 14 04:28:33 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201024 kb
Host smart-a425f841-0d09-4c29-8b3f-59d757f38dc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144326306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.1144326306
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2661928636
Short name T149
Test name
Test status
Simulation time 40266643 ps
CPU time 0.72 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 199660 kb
Host smart-264e578d-7084-4aa6-a9a9-a40371149b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661928636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.2661928636
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3581336642
Short name T12
Test name
Test status
Simulation time 49544131 ps
CPU time 1.03 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 201080 kb
Host smart-e15945df-facd-497e-a436-59a538296673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581336642 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.3581336642
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2694488047
Short name T57
Test name
Test status
Simulation time 125543869 ps
CPU time 1.75 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 201552 kb
Host smart-5c88852c-3a10-4849-bfdc-3532e44b8b17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694488047 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.2694488047
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2190319976
Short name T63
Test name
Test status
Simulation time 84600764 ps
CPU time 1.62 seconds
Started Aug 14 04:28:53 PM PDT 24
Finished Aug 14 04:28:55 PM PDT 24
Peak memory 201636 kb
Host smart-e8ac5421-fba3-45fd-9bd4-0358b7b166d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190319976 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.2190319976
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1945833201
Short name T105
Test name
Test status
Simulation time 80736944 ps
CPU time 2.7 seconds
Started Aug 14 04:28:47 PM PDT 24
Finished Aug 14 04:28:50 PM PDT 24
Peak memory 201252 kb
Host smart-72840d4b-0ac9-493b-bcd6-6396d3636309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945833201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.1945833201
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1787689106
Short name T29
Test name
Test status
Simulation time 121552316 ps
CPU time 1.73 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 201352 kb
Host smart-8ed5b49a-d6c8-4347-b3d8-9010544345f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787689106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.1787689106
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.301138117
Short name T136
Test name
Test status
Simulation time 25992444 ps
CPU time 0.91 seconds
Started Aug 14 04:28:38 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 201088 kb
Host smart-ae2fb27b-54b9-4cbb-8972-845f491bc7c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301138117 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.301138117
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.3886252083
Short name T25
Test name
Test status
Simulation time 21006237 ps
CPU time 0.82 seconds
Started Aug 14 04:28:55 PM PDT 24
Finished Aug 14 04:28:56 PM PDT 24
Peak memory 200960 kb
Host smart-a62c351b-2836-49a2-8cc2-790f147e6243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886252083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.3886252083
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2866071515
Short name T156
Test name
Test status
Simulation time 10954088 ps
CPU time 0.64 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:33 PM PDT 24
Peak memory 199660 kb
Host smart-148918b3-7fc1-475d-a789-9c0b53636afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866071515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.2866071515
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.4244004925
Short name T142
Test name
Test status
Simulation time 24558524 ps
CPU time 0.99 seconds
Started Aug 14 04:28:33 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201124 kb
Host smart-6d9f9898-dd27-4147-af4a-4d2e8448eb1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244004925 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.4244004925
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1485467047
Short name T60
Test name
Test status
Simulation time 483851662 ps
CPU time 2.5 seconds
Started Aug 14 04:28:56 PM PDT 24
Finished Aug 14 04:28:58 PM PDT 24
Peak memory 201612 kb
Host smart-4f178dff-adce-461c-ae7b-f8be40b6247f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485467047 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.1485467047
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.251127440
Short name T69
Test name
Test status
Simulation time 142195820 ps
CPU time 2.73 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 209768 kb
Host smart-5c06367f-1475-4b16-87c4-917d9c7a0094
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251127440 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.251127440
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.356967235
Short name T148
Test name
Test status
Simulation time 52689128 ps
CPU time 1.88 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 201308 kb
Host smart-219fccf0-ec93-4d30-af79-2087d3296cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356967235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm
gr_tl_errors.356967235
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1359218533
Short name T28
Test name
Test status
Simulation time 353034609 ps
CPU time 3.2 seconds
Started Aug 14 04:28:43 PM PDT 24
Finished Aug 14 04:28:46 PM PDT 24
Peak memory 201332 kb
Host smart-954cce09-fca4-4fce-8839-9e8ac94881fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359218533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.1359218533
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2107262034
Short name T23
Test name
Test status
Simulation time 31751969 ps
CPU time 1.03 seconds
Started Aug 14 04:28:51 PM PDT 24
Finished Aug 14 04:28:52 PM PDT 24
Peak memory 200736 kb
Host smart-24a2503a-c1aa-469f-925b-dea8f7d012fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107262034 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.2107262034
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.142467918
Short name T181
Test name
Test status
Simulation time 38983580 ps
CPU time 0.78 seconds
Started Aug 14 04:28:50 PM PDT 24
Finished Aug 14 04:28:51 PM PDT 24
Peak memory 201024 kb
Host smart-61acace6-65e1-4ade-b787-84e7dceec705
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142467918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.c
lkmgr_csr_rw.142467918
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3984608029
Short name T110
Test name
Test status
Simulation time 11851053 ps
CPU time 0.66 seconds
Started Aug 14 04:28:31 PM PDT 24
Finished Aug 14 04:28:32 PM PDT 24
Peak memory 199624 kb
Host smart-215de8eb-25aa-4b96-90e8-b1b0f0933dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984608029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3984608029
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2823140183
Short name T147
Test name
Test status
Simulation time 101005466 ps
CPU time 1.12 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201080 kb
Host smart-28201239-1681-4a8f-8e74-62d94381549c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823140183 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.2823140183
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3407567448
Short name T67
Test name
Test status
Simulation time 210700492 ps
CPU time 2.19 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 201544 kb
Host smart-8042ba6e-6e67-4b6c-9ebe-6be48ce1cd73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407567448 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.3407567448
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.975185572
Short name T115
Test name
Test status
Simulation time 931326878 ps
CPU time 4.73 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:35 PM PDT 24
Peak memory 217820 kb
Host smart-fc5b9120-3f8a-4187-8f61-be1edefe2eee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975185572 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.975185572
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2599142150
Short name T21
Test name
Test status
Simulation time 144475677 ps
CPU time 2.68 seconds
Started Aug 14 04:28:51 PM PDT 24
Finished Aug 14 04:28:53 PM PDT 24
Peak memory 200812 kb
Host smart-5bc2432c-988a-4061-a4bc-de9985acb1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599142150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.2599142150
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3646562938
Short name T7
Test name
Test status
Simulation time 21510416 ps
CPU time 1.03 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 201188 kb
Host smart-c92ff15e-390d-42b9-bebb-f8fa537cf410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646562938 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.3646562938
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3996574015
Short name T131
Test name
Test status
Simulation time 58065159 ps
CPU time 0.88 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 200972 kb
Host smart-e80d5249-9721-4433-a2e3-19f2f7eb67a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996574015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.3996574015
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3230441497
Short name T182
Test name
Test status
Simulation time 14506406 ps
CPU time 0.68 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 199572 kb
Host smart-579d71f2-88ef-4e19-a1ae-3aa204495486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230441497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.3230441497
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.559962693
Short name T197
Test name
Test status
Simulation time 34955057 ps
CPU time 1.01 seconds
Started Aug 14 04:28:24 PM PDT 24
Finished Aug 14 04:28:25 PM PDT 24
Peak memory 201076 kb
Host smart-905969d7-5f03-4cb9-b4e4-c19dd702461a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559962693 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.clkmgr_same_csr_outstanding.559962693
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1213210807
Short name T66
Test name
Test status
Simulation time 123168911 ps
CPU time 1.84 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 201592 kb
Host smart-cca49698-68df-4f96-9600-111c3f6588e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213210807 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.1213210807
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1039648458
Short name T133
Test name
Test status
Simulation time 139419754 ps
CPU time 1.94 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 209664 kb
Host smart-7222cbf6-ea11-42f5-9ccc-a143f03980ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039648458 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.1039648458
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3451489508
Short name T38
Test name
Test status
Simulation time 243148653 ps
CPU time 3.48 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:46 PM PDT 24
Peak memory 201324 kb
Host smart-f9b9ffdf-6700-4576-b1fb-6cc5f75f4336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451489508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.3451489508
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.282633276
Short name T41
Test name
Test status
Simulation time 105120456 ps
CPU time 1.67 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201300 kb
Host smart-00d3b19a-b3f7-4ec8-8a5a-065404542c24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282633276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_tl_intg_err.282633276
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1232265013
Short name T81
Test name
Test status
Simulation time 49630780 ps
CPU time 0.94 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:35 PM PDT 24
Peak memory 201204 kb
Host smart-4ca95d29-27e2-4358-b7a8-ef8bd3eccf0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232265013 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.1232265013
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2228174975
Short name T111
Test name
Test status
Simulation time 24817002 ps
CPU time 0.77 seconds
Started Aug 14 04:28:48 PM PDT 24
Finished Aug 14 04:28:49 PM PDT 24
Peak memory 201028 kb
Host smart-1e74f848-c5cd-4992-9053-15a0c7d5f328
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228174975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.2228174975
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1281203627
Short name T205
Test name
Test status
Simulation time 12402475 ps
CPU time 0.66 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:40 PM PDT 24
Peak memory 199612 kb
Host smart-85ae8204-aeac-4e0f-b81e-1237a671422c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281203627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.1281203627
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2316300505
Short name T201
Test name
Test status
Simulation time 31640369 ps
CPU time 1.17 seconds
Started Aug 14 04:28:35 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 201100 kb
Host smart-0ae01fda-973a-46ee-adfe-4a1fb7e4c1ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316300505 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.2316300505
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2051107772
Short name T51
Test name
Test status
Simulation time 389519112 ps
CPU time 2.44 seconds
Started Aug 14 04:29:02 PM PDT 24
Finished Aug 14 04:29:05 PM PDT 24
Peak memory 201572 kb
Host smart-feb983da-28e8-452c-bb35-a36f78908dac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051107772 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.2051107772
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.442190764
Short name T145
Test name
Test status
Simulation time 60844893 ps
CPU time 1.53 seconds
Started Aug 14 04:28:53 PM PDT 24
Finished Aug 14 04:28:55 PM PDT 24
Peak memory 201624 kb
Host smart-47bf870a-4391-4d6a-a80b-d796a4a7a45b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442190764 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.442190764
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.4283266875
Short name T31
Test name
Test status
Simulation time 59380665 ps
CPU time 1.61 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 201280 kb
Host smart-1a16e734-f8c2-4617-9c9f-ae82eb84091d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283266875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.4283266875
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2002784572
Short name T44
Test name
Test status
Simulation time 411722364 ps
CPU time 3.33 seconds
Started Aug 14 04:28:41 PM PDT 24
Finished Aug 14 04:28:44 PM PDT 24
Peak memory 201220 kb
Host smart-a100f15e-2f51-485d-946e-0f09cb967267
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002784572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.2002784572
Directory /workspace/9.clkmgr_tl_intg_err/latest
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