Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	190022	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

418474

1

T7

27

T9

2

T26

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	182423	1			T7	36		T8	50		T9	1
values[0x0]	202655	1			T7	10		T9	1		T26	33
values[0x1]	223418	1			T7	17		T9	2		T26	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	133395	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

475101

1

T7

31

T8

16

T9

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3157	1			T8	1		T26	2		T1	2
valid_sources[0x01]	2146	1			T6	1		T1	2		T4	2
valid_sources[0x02]	2835	1			T8	2		T4	2		T2	24
valid_sources[0x03]	2165	1			T27	1		T6	1		T4	6
valid_sources[0x04]	2103	1			T6	3		T1	5		T4	2
valid_sources[0x05]	2561	1			T4	6		T2	6		T33	1
valid_sources[0x06]	1817	1			T5	1		T4	4		T2	6
valid_sources[0x07]	2089	1			T27	1		T4	2		T2	4
valid_sources[0x08]	2019	1			T6	4		T1	2		T4	4
valid_sources[0x09]	3195	1			T5	1		T1	2		T4	1
valid_sources[0x0a]	2292	1			T6	6		T1	1		T4	2
valid_sources[0x0b]	2474	1			T5	1		T4	2		T2	5
valid_sources[0x0c]	2728	1			T8	1		T4	6		T2	1
valid_sources[0x0d]	2346	1			T26	2		T1	3		T4	5
valid_sources[0x0e]	2372	1			T5	1		T4	2		T2	10
valid_sources[0x0f]	2835	1			T6	3		T1	1		T4	3
valid_sources[0x10]	1879	1			T6	1		T4	4		T2	16
valid_sources[0x11]	2165	1			T8	1		T5	2		T1	5
valid_sources[0x12]	2174	1			T26	1		T1	3		T4	1
valid_sources[0x13]	2751	1			T4	5		T41	1		T35	6
valid_sources[0x14]	3059	1			T1	1		T4	3		T2	1
valid_sources[0x15]	1927	1			T27	1		T6	2		T4	3
valid_sources[0x16]	2272	1			T27	3		T6	6		T1	1
valid_sources[0x17]	2250	1			T8	2		T5	1		T4	3
valid_sources[0x18]	2347	1			T26	2		T27	1		T6	3
valid_sources[0x19]	2124	1			T8	1		T27	2		T5	1
valid_sources[0x1a]	2442	1			T8	1		T26	3		T4	3
valid_sources[0x1b]	2420	1			T9	2		T26	3		T6	1
valid_sources[0x1c]	4579	1			T5	1		T6	7		T4	1
valid_sources[0x1d]	2309	1			T6	2		T1	6		T4	6
valid_sources[0x1e]	3479	1			T7	63		T5	1		T1	3
valid_sources[0x1f]	2293	1			T5	2		T6	3		T1	5
valid_sources[0x20]	2298	1			T4	2		T80	2		T34	1
valid_sources[0x21]	1875	1			T1	1		T2	3		T34	1
valid_sources[0x22]	2210	1			T4	2		T2	5		T34	3
valid_sources[0x23]	2282	1			T6	3		T1	2		T4	4
valid_sources[0x24]	2421	1			T5	1		T4	3		T2	1
valid_sources[0x25]	2617	1			T27	2		T34	1		T35	2
valid_sources[0x26]	2649	1			T27	2		T6	1		T1	9
valid_sources[0x27]	3850	1			T8	1		T5	1		T6	2
valid_sources[0x28]	2646	1			T1	4		T4	2		T2	13
valid_sources[0x29]	2432	1			T4	3		T2	7		T33	2
valid_sources[0x2a]	2223	1			T27	2		T6	1		T1	4
valid_sources[0x2b]	2731	1			T26	2		T27	2		T6	2
valid_sources[0x2c]	2013	1			T8	2		T27	1		T6	2
valid_sources[0x2d]	2150	1			T27	2		T1	1		T4	5
valid_sources[0x2e]	2308	1			T27	1		T6	4		T4	3
valid_sources[0x2f]	2213	1			T26	1		T27	1		T4	4
valid_sources[0x30]	2248	1			T26	11		T4	1		T2	8
valid_sources[0x31]	2071	1			T26	8		T4	3		T34	1
valid_sources[0x32]	2291	1			T27	1		T6	2		T1	2
valid_sources[0x33]	2597	1			T27	3		T4	6		T2	4
valid_sources[0x34]	2112	1			T4	4		T2	14		T34	6
valid_sources[0x35]	2400	1			T6	3		T4	6		T2	19
valid_sources[0x36]	2360	1			T27	1		T4	1		T2	18
valid_sources[0x37]	2014	1			T8	1		T6	2		T1	1
valid_sources[0x38]	2381	1			T8	1		T6	4		T4	2
valid_sources[0x39]	2358	1			T27	2		T5	1		T4	5
valid_sources[0x3a]	2511	1			T5	1		T1	5		T4	1
valid_sources[0x3b]	2109	1			T1	9		T4	6		T2	3
valid_sources[0x3c]	2235	1			T8	2		T6	8		T1	8
valid_sources[0x3d]	2221	1			T5	1		T1	1		T4	3
valid_sources[0x3e]	2274	1			T27	1		T1	3		T4	1
valid_sources[0x3f]	2265	1			T27	3		T4	3		T2	3
valid_sources[0x40]	2075	1			T6	2		T1	1		T4	2
valid_sources[0x41]	2321	1			T27	2		T5	1		T34	1
valid_sources[0x42]	2032	1			T26	6		T29	19		T6	2
valid_sources[0x43]	2764	1			T1	1		T2	2		T32	3
valid_sources[0x44]	2153	1			T27	3		T5	1		T6	8
valid_sources[0x45]	2055	1			T8	1		T5	1		T1	6
valid_sources[0x46]	2403	1			T27	1		T4	3		T41	1
valid_sources[0x47]	2022	1			T1	5		T4	3		T2	5
valid_sources[0x48]	2186	1			T6	5		T1	10		T4	5
valid_sources[0x49]	2274	1			T27	1		T5	3		T1	1
valid_sources[0x4a]	1883	1			T26	6		T4	1		T2	1
valid_sources[0x4b]	2385	1			T26	1		T5	1		T4	1
valid_sources[0x4c]	2306	1			T27	2		T5	1		T1	4
valid_sources[0x4d]	2386	1			T8	1		T26	2		T27	1
valid_sources[0x4e]	2204	1			T1	4		T4	1		T2	16
valid_sources[0x4f]	2090	1			T26	5		T5	2		T4	5
valid_sources[0x50]	2280	1			T26	2		T4	4		T2	10
valid_sources[0x51]	2145	1			T4	5		T33	4		T34	1
valid_sources[0x52]	1912	1			T1	2		T4	2		T35	6
valid_sources[0x53]	1896	1			T4	9		T2	23		T32	26
valid_sources[0x54]	2782	1			T4	3		T33	4		T34	3
valid_sources[0x55]	1997	1			T6	6		T4	4		T2	2
valid_sources[0x56]	1942	1			T8	1		T6	1		T1	3
valid_sources[0x57]	1968	1			T8	1		T27	2		T6	3
valid_sources[0x58]	2680	1			T5	1		T1	1		T4	4
valid_sources[0x59]	2044	1			T8	1		T27	1		T5	1
valid_sources[0x5a]	2427	1			T8	1		T5	2		T4	3
valid_sources[0x5b]	2253	1			T27	1		T4	2		T2	26
valid_sources[0x5c]	2316	1			T4	3		T2	14		T33	1
valid_sources[0x5d]	1974	1			T1	1		T4	1		T2	7
valid_sources[0x5e]	2440	1			T8	2		T6	2		T2	4
valid_sources[0x5f]	2145	1			T26	1		T4	5		T2	3
valid_sources[0x60]	2291	1			T4	3		T2	21		T114	20
valid_sources[0x61]	2507	1			T5	2		T4	1		T2	30
valid_sources[0x62]	2390	1			T27	2		T4	1		T2	6
valid_sources[0x63]	2514	1			T26	2		T5	1		T19	1
valid_sources[0x64]	2530	1			T27	2		T4	5		T2	3
valid_sources[0x65]	2379	1			T2	7		T33	1		T34	2
valid_sources[0x66]	2263	1			T1	5		T4	4		T80	1
valid_sources[0x67]	2501	1			T4	3		T2	13		T35	1
valid_sources[0x68]	2463	1			T27	2		T1	7		T4	2
valid_sources[0x69]	2353	1			T8	1		T26	1		T27	2
valid_sources[0x6a]	2139	1			T26	5		T5	1		T4	3
valid_sources[0x6b]	2619	1			T8	1		T26	1		T5	2
valid_sources[0x6c]	2350	1			T1	1		T19	1		T4	3
valid_sources[0x6d]	2302	1			T4	5		T32	4		T125	1
valid_sources[0x6e]	2417	1			T27	1		T4	4		T34	2
valid_sources[0x6f]	2281	1			T2	17		T34	1		T35	6
valid_sources[0x70]	2227	1			T5	1		T6	3		T4	3
valid_sources[0x71]	2238	1			T4	2		T34	8		T35	2
valid_sources[0x72]	2021	1			T4	1		T170	1		T12	4
valid_sources[0x73]	2367	1			T26	1		T5	1		T1	1
valid_sources[0x74]	3612	1			T5	2		T6	7		T4	4
valid_sources[0x75]	4459	1			T5	1		T6	9		T1	4
valid_sources[0x76]	2751	1			T27	1		T20	4		T4	2
valid_sources[0x77]	2202	1			T27	4		T5	1		T6	10
valid_sources[0x78]	2339	1			T27	1		T6	3		T1	1
valid_sources[0x79]	2390	1			T27	1		T4	4		T22	17
valid_sources[0x7a]	2363	1			T6	1		T1	1		T24	2
valid_sources[0x7b]	2809	1			T1	2		T2	3		T41	1
valid_sources[0x7c]	2943	1			T4	3		T2	2		T114	1
valid_sources[0x7d]	2113	1			T6	14		T4	1		T24	2
valid_sources[0x7e]	1864	1			T5	1		T1	4		T4	4
valid_sources[0x7f]	2504	1			T8	1		T1	4		T4	2
valid_sources[0x80]	2419	1			T8	1		T6	1		T1	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

119955

1

T7

25

T9

1

T26

34

values[0x0]

all_enables

biggest_size

160745

1

T7

2

T9

1

T26

11

values[0x1]

all_enables

biggest_size

137774

1

T26

6

T27

2

T29

1