Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T4
0	1	Covered	T2,T43,T169
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T2
1	0	Covered	T28,T23,T40
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	167074840	7101	0	0
GateOpen_A	167074840	13311	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167074840	7101	0	0
T1	536334	0	0	0
T2	0	53	0	0
T4	190939	0	0	0
T5	74117	0	0	0
T6	327813	0	0	0
T12	0	11	0	0
T13	0	88	0	0
T14	0	7	0	0
T19	9084	0	0	0
T20	3060	0	0	0
T21	14844	0	0	0
T22	3336	0	0	0
T23	0	13	0	0
T28	5587	5	0	0
T29	9439	0	0	0
T40	0	16	0	0
T42	0	4	0	0
T43	0	3	0	0
T169	0	4	0	0
T170	0	16	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167074840	13311	0	0
T1	536334	0	0	0
T4	0	68	0	0
T5	74117	4	0	0
T6	327813	0	0	0
T8	320133	204	0	0
T9	18117	4	0	0
T19	9084	4	0	0
T20	0	4	0	0
T21	0	4	0	0
T23	0	17	0	0
T26	6206	4	0	0
T27	18122	0	0	0
T28	5587	9	0	0
T29	9439	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T4
0	1	Covered	T2,T43,T169
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T2
1	0	Covered	T28,T23,T40
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	18041955	1726	0	0
GateOpen_A	18041955	3272	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041955	1726	0	0
T1	59570	0	0	0
T2	0	11	0	0
T4	12799	0	0	0
T5	8229	0	0	0
T6	36401	0	0	0
T12	0	2	0	0
T13	0	22	0	0
T14	0	7	0	0
T19	1012	0	0	0
T20	332	0	0	0
T21	1839	0	0	0
T22	351	0	0	0
T23	0	3	0	0
T28	616	1	0	0
T29	1079	0	0	0
T40	0	4	0	0
T42	0	1	0	0
T169	0	1	0	0
T170	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041955	3272	0	0
T1	59570	0	0	0
T4	0	17	0	0
T5	8229	1	0	0
T6	36401	0	0	0
T8	34855	51	0	0
T9	2002	1	0	0
T19	1012	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	4	0	0
T26	670	1	0	0
T27	2010	0	0	0
T28	616	2	0	0
T29	1079	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T4
0	1	Covered	T2,T43,T169
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T2
1	0	Covered	T28,T23,T40
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	36084245	1796	0	0
GateOpen_A	36084245	3344	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36084245	1796	0	0
T1	119139	0	0	0
T2	0	13	0	0
T4	25598	0	0	0
T5	16458	0	0	0
T6	72802	0	0	0
T12	0	3	0	0
T13	0	24	0	0
T19	2023	0	0	0
T20	663	0	0	0
T21	3677	0	0	0
T22	701	0	0	0
T23	0	3	0	0
T28	1231	1	0	0
T29	2157	0	0	0
T40	0	4	0	0
T42	0	1	0	0
T43	0	1	0	0
T169	0	1	0	0
T170	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36084245	3344	0	0
T1	119139	0	0	0
T4	0	17	0	0
T5	16458	1	0	0
T6	72802	0	0	0
T8	69700	51	0	0
T9	4003	1	0	0
T19	2023	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	4	0	0
T26	1339	1	0	0
T27	4019	0	0	0
T28	1231	2	0	0
T29	2157	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T4
0	1	Covered	T2,T43,T169
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T2
1	0	Covered	T28,T23,T40
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	73939765	1779	0	0
GateOpen_A	73939765	3337	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939765	1779	0	0
T1	238413	0	0	0
T2	0	12	0	0
T4	101693	0	0	0
T5	32953	0	0	0
T6	145738	0	0	0
T12	0	3	0	0
T13	0	21	0	0
T19	4032	0	0	0
T20	1376	0	0	0
T21	6218	0	0	0
T22	1523	0	0	0
T23	0	3	0	0
T28	2555	1	0	0
T29	4135	0	0	0
T40	0	4	0	0
T42	0	1	0	0
T43	0	1	0	0
T169	0	1	0	0
T170	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939765	3337	0	0
T1	238413	0	0	0
T4	0	17	0	0
T5	32953	1	0	0
T6	145738	0	0	0
T8	143716	51	0	0
T9	8074	1	0	0
T19	4032	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	4	0	0
T26	2798	1	0	0
T27	8062	0	0	0
T28	2555	2	0	0
T29	4135	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T4
0	1	Covered	T2,T43,T169
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T2
1	0	Covered	T28,T23,T40
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	39008875	1800	0	0
GateOpen_A	39008875	3358	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39008875	1800	0	0
T1	119212	0	0	0
T2	0	17	0	0
T4	50849	0	0	0
T5	16477	0	0	0
T6	72872	0	0	0
T12	0	3	0	0
T13	0	21	0	0
T19	2017	0	0	0
T20	689	0	0	0
T21	3110	0	0	0
T22	761	0	0	0
T23	0	4	0	0
T28	1185	2	0	0
T29	2068	0	0	0
T40	0	4	0	0
T42	0	1	0	0
T43	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39008875	3358	0	0
T1	119212	0	0	0
T4	0	17	0	0
T5	16477	1	0	0
T6	72872	0	0	0
T8	71862	51	0	0
T9	4038	1	0	0
T19	2017	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	5	0	0
T26	1399	1	0	0
T27	4031	0	0	0
T28	1185	3	0	0
T29	2068	0	0	0