Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	180121540	31064	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180121540	31064	0	0
T1	335280	145	0	0
T2	721455	343	0	0
T3	0	284	0	0
T4	328395	0	0	0
T12	0	715	0	0
T13	0	187	0	0
T14	0	431	0	0
T15	0	125	0	0
T16	0	227	0	0
T17	0	243	0	0
T18	0	519	0	0
T19	5035	0	0	0
T20	6955	0	0	0
T21	7770	0	0	0
T22	7610	0	0	0
T23	5065	0	0	0
T24	4340	0	0	0
T25	6730	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36024308	4508	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	4508	0	0
T1	67056	22	0	0
T2	144291	54	0	0
T3	0	41	0	0
T4	65679	0	0	0
T12	0	93	0	0
T13	0	24	0	0
T14	0	58	0	0
T15	0	19	0	0
T16	0	36	0	0
T17	0	34	0	0
T18	0	83	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T24	868	0	0	0
T25	1346	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36024308	4514	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	4514	0	0
T1	67056	22	0	0
T2	144291	55	0	0
T3	0	41	0	0
T4	65679	0	0	0
T12	0	104	0	0
T13	0	27	0	0
T14	0	54	0	0
T15	0	18	0	0
T16	0	36	0	0
T17	0	34	0	0
T18	0	82	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T24	868	0	0	0
T25	1346	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36024308	6229	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	6229	0	0
T1	67056	31	0	0
T2	144291	70	0	0
T3	0	58	0	0
T4	65679	0	0	0
T12	0	141	0	0
T13	0	37	0	0
T14	0	85	0	0
T15	0	25	0	0
T16	0	46	0	0
T17	0	48	0	0
T18	0	105	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T24	868	0	0	0
T25	1346	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36024308	6206	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	6206	0	0
T1	67056	30	0	0
T2	144291	69	0	0
T3	0	54	0	0
T4	65679	0	0	0
T12	0	141	0	0
T13	0	37	0	0
T14	0	84	0	0
T15	0	24	0	0
T16	0	46	0	0
T17	0	48	0	0
T18	0	105	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T24	868	0	0	0
T25	1346	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36024308	9607	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	9607	0	0
T1	67056	40	0	0
T2	144291	95	0	0
T3	0	90	0	0
T4	65679	0	0	0
T12	0	236	0	0
T13	0	62	0	0
T14	0	150	0	0
T15	0	39	0	0
T16	0	63	0	0
T17	0	79	0	0
T18	0	144	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T24	868	0	0	0
T25	1346	0	0	0