Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T8,T4,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	36024308	33339109	0	0
AllClkBypReqTrue_A	36024308	80574	0	0
IoClkBypReqFalse_A	36024308	33285123	0	2415
IoClkBypReqTrue_A	36024308	130130	0	0
LcClkBypAckFalse_A	36024308	33344737	0	0
LcClkBypAckTrue_A	36024308	74946	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	33339109	0	0
T1	67056	66990	0	0
T5	8581	8534	0	0
T6	174536	174318	0	0
T7	1600	1581	0	0
T8	7484	7012	0	0
T9	672	657	0	0
T26	2856	2606	0	0
T27	2014	1994	0	0
T28	1237	1159	0	0
T29	1033	933	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	80574	0	0
T1	67056	0	0	0
T4	65679	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T19	1007	41	0	0
T20	1391	0	0	0
T21	1554	214	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T29	1033	45	0	0
T41	0	65	0	0
T79	0	101	0	0
T80	0	150	0	0
T114	0	274	0	0
T123	0	57	0	0
T124	0	233	0	0
T125	0	62	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	33285123	0	2415
T1	67056	66988	0	3
T5	8581	8532	0	3
T6	174536	174316	0	3
T7	1600	1579	0	3
T8	7484	6910	0	3
T9	672	631	0	3
T26	2856	2604	0	3
T27	2014	1992	0	3
T28	1237	1157	0	3
T29	1033	917	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	130130	0	0
T1	67056	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T9	672	24	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	0	340	0	0
T26	2856	0	0	0
T27	2014	0	0	0
T28	1237	0	0	0
T29	1033	59	0	0
T41	0	191	0	0
T79	0	155	0	0
T80	0	204	0	0
T114	0	613	0	0
T123	0	54	0	0
T124	0	299	0	0
T126	0	666	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	33344737	0	0
T1	67056	66990	0	0
T5	8581	8534	0	0
T6	174536	174318	0	0
T7	1600	1581	0	0
T8	7484	7012	0	0
T9	672	657	0	0
T26	2856	2606	0	0
T27	2014	1994	0	0
T28	1237	1159	0	0
T29	1033	929	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	74946	0	0
T1	67056	0	0	0
T4	65679	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T12	0	61	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	258	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T29	1033	49	0	0
T41	0	122	0	0
T79	0	82	0	0
T80	0	109	0	0
T114	0	376	0	0
T123	0	20	0	0
T124	0	176	0	0
T126	0	284	0	0