Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	324312716	8839	0	0
TransStop_A	324312716	4614	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324312716	8839	0	0
T1	993416	0	0	0
T2	0	8	0	0
T5	137308	0	0	0
T6	655264	0	0	0
T7	80044	19	0	0
T8	598836	0	0	0
T9	33648	0	0	0
T12	0	106	0	0
T13	0	47	0	0
T20	0	2	0	0
T26	11660	36	0	0
T27	33592	41	0	0
T28	10020	0	0	0
T29	17228	0	0	0
T42	0	4	0	0
T43	0	13	0	0
T75	0	22	0	0
T127	0	26	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324312716	4614	0	0
T1	993416	0	0	0
T2	0	8	0	0
T5	137308	0	0	0
T6	655264	0	0	0
T7	80044	10	0	0
T8	598836	0	0	0
T9	33648	0	0	0
T12	0	47	0	0
T13	0	28	0	0
T20	0	2	0	0
T26	11660	14	0	0
T27	33592	22	0	0
T28	10020	0	0	0
T29	17228	0	0	0
T42	0	4	0	0
T43	0	6	0	0
T75	0	15	0	0
T127	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81078179	2245	0	0
TransStop_A	81078179	1183	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81078179	2245	0	0
T1	248354	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163816	0	0	0
T7	20011	4	0	0
T8	149709	0	0	0
T9	8412	0	0	0
T12	0	29	0	0
T13	0	10	0	0
T26	2915	9	0	0
T27	8398	14	0	0
T28	2505	0	0	0
T29	4307	0	0	0
T42	0	1	0	0
T43	0	6	0	0
T75	0	10	0	0
T127	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81078179	1183	0	0
T1	248354	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163816	0	0	0
T7	20011	2	0	0
T8	149709	0	0	0
T9	8412	0	0	0
T12	0	11	0	0
T13	0	6	0	0
T26	2915	3	0	0
T27	8398	7	0	0
T28	2505	0	0	0
T29	4307	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T75	0	6	0	0
T127	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81078179	2190	0	0
TransStop_A	81078179	1155	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81078179	2190	0	0
T1	248354	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163816	0	0	0
T7	20011	6	0	0
T8	149709	0	0	0
T9	8412	0	0	0
T12	0	21	0	0
T13	0	10	0	0
T26	2915	10	0	0
T27	8398	10	0	0
T28	2505	0	0	0
T29	4307	0	0	0
T42	0	1	0	0
T43	0	4	0	0
T75	0	12	0	0
T127	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81078179	1155	0	0
T1	248354	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163816	0	0	0
T7	20011	3	0	0
T8	149709	0	0	0
T9	8412	0	0	0
T12	0	10	0	0
T13	0	8	0	0
T26	2915	4	0	0
T27	8398	6	0	0
T28	2505	0	0	0
T29	4307	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T75	0	9	0	0
T127	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81078179	2212	0	0
TransStop_A	81078179	1149	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81078179	2212	0	0
T1	248354	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163816	0	0	0
T7	20011	4	0	0
T8	149709	0	0	0
T9	8412	0	0	0
T12	0	28	0	0
T13	0	14	0	0
T20	0	1	0	0
T26	2915	11	0	0
T27	8398	7	0	0
T28	2505	0	0	0
T29	4307	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T127	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81078179	1149	0	0
T1	248354	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163816	0	0	0
T7	20011	1	0	0
T8	149709	0	0	0
T9	8412	0	0	0
T12	0	14	0	0
T13	0	8	0	0
T20	0	1	0	0
T26	2915	5	0	0
T27	8398	3	0	0
T28	2505	0	0	0
T29	4307	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T127	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81078179	2192	0	0
TransStop_A	81078179	1127	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81078179	2192	0	0
T1	248354	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163816	0	0	0
T7	20011	5	0	0
T8	149709	0	0	0
T9	8412	0	0	0
T12	0	28	0	0
T13	0	13	0	0
T20	0	1	0	0
T26	2915	6	0	0
T27	8398	10	0	0
T28	2505	0	0	0
T29	4307	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T127	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81078179	1127	0	0
T1	248354	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163816	0	0	0
T7	20011	4	0	0
T8	149709	0	0	0
T9	8412	0	0	0
T12	0	12	0	0
T13	0	6	0	0
T20	0	1	0	0
T26	2915	2	0	0
T27	8398	6	0	0
T28	2505	0	0	0
T29	4307	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T127	0	2	0	0