Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	36024308	3087289	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	3087289	0	60
T1	67056	10998	0	1
T2	0	22281	0	0
T3	0	28936	0	1
T4	65679	0	0	0
T5	8581	680	0	1
T6	174536	0	0	0
T12	0	87068	0	1
T13	0	13161	0	0
T14	0	49767	0	1
T15	0	11964	0	0
T16	0	16245	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T24	868	0	0	0
T31	0	0	0	1
T33	0	1299	0	1
T38	0	0	0	1
T82	0	0	0	1
T128	0	0	0	1