Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	36936112	421248	0	0
clk_enables_rd_A	36936112	10100	0	0
clk_hints_rd_A	36936112	9733	0	0
extclk_ctrl_rd_A	36936112	12366	0	0
extclk_ctrl_regwen_rd_A	36936112	7438	0	0
jitter_enable_rd_A	36936112	19086	0	0
jitter_regwen_rd_A	36936112	7724	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36936112	421248	0	0
T13	307171	8405	0	0
T14	162209	0	0	0
T15	478384	14726	0	0
T16	255990	7261	0	0
T17	0	4013	0	0
T30	0	15523	0	0
T37	0	4825	0	0
T69	0	2926	0	0
T70	0	8121	0	0
T71	0	6304	0	0
T72	0	9637	0	0
T73	1807	0	0	0
T74	1360	0	0	0
T75	3712	0	0	0
T76	2434	0	0	0
T77	2303	0	0	0
T78	957	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36936112	10100	0	0
T13	307171	324	0	0
T14	162209	0	0	0
T15	478384	757	0	0
T16	255990	320	0	0
T17	0	105	0	0
T37	0	171	0	0
T71	0	194	0	0
T72	0	253	0	0
T73	1807	0	0	0
T74	1360	0	0	0
T75	3712	0	0	0
T76	2434	0	0	0
T77	2303	0	0	0
T78	957	0	0	0
T151	0	232	0	0
T152	0	7	0	0
T153	0	7	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36936112	9733	0	0
T13	307171	362	0	0
T14	162209	0	0	0
T15	478384	520	0	0
T16	255990	305	0	0
T17	0	87	0	0
T37	0	203	0	0
T71	0	283	0	0
T72	0	172	0	0
T73	1807	0	0	0
T74	1360	0	0	0
T75	3712	0	0	0
T76	2434	0	0	0
T77	2303	0	0	0
T78	957	0	0	0
T151	0	230	0	0
T152	0	1	0	0
T153	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36936112	12366	0	0
T2	144291	0	0	0
T4	65679	0	0	0
T13	0	615	0	0
T15	0	916	0	0
T16	0	810	0	0
T17	0	90	0	0
T21	1554	23	0	0
T22	1522	0	0	0
T23	1013	0	0	0
T24	868	0	0	0
T25	1346	0	0	0
T32	70972	0	0	0
T41	1709	0	0	0
T79	1819	0	0	0
T114	0	50	0	0
T124	0	50	0	0
T126	0	57	0	0
T154	0	3	0	0
T155	0	46	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36936112	7438	0	0
T13	307171	311	0	0
T14	162209	0	0	0
T15	478384	582	0	0
T16	255990	273	0	0
T17	0	81	0	0
T37	0	127	0	0
T71	0	268	0	0
T72	0	218	0	0
T73	1807	0	0	0
T74	1360	0	0	0
T75	3712	0	0	0
T76	2434	0	0	0
T77	2303	0	0	0
T78	957	0	0	0
T151	0	231	0	0
T156	0	38	0	0
T157	0	19	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36936112	19086	0	0
T13	307171	886	0	0
T14	162209	0	0	0
T15	478384	1096	0	0
T16	255990	1352	0	0
T17	0	150	0	0
T37	0	938	0	0
T71	0	1167	0	0
T72	0	683	0	0
T73	1807	0	0	0
T74	1360	0	0	0
T75	3712	0	0	0
T76	2434	0	0	0
T77	2303	0	0	0
T78	957	0	0	0
T151	0	294	0	0
T152	0	111	0	0
T158	0	103	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36936112	7724	0	0
T13	307171	372	0	0
T14	162209	0	0	0
T15	478384	580	0	0
T16	255990	267	0	0
T17	0	110	0	0
T37	0	199	0	0
T71	0	247	0	0
T72	0	216	0	0
T73	1807	0	0	0
T74	1360	0	0	0
T75	3712	0	0	0
T76	2434	0	0	0
T77	2303	0	0	0
T78	957	0	0	0
T151	0	218	0	0
T159	0	365	0	0
T160	0	255	0	0