Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T26
1	0	Covered	T19,T21,T41
1	1	Covered	T9,T29,T19

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	73939765	2843	0	0
g_div2.Div2Whole_A	73939765	3364	0	0
g_div4.Div4Stepped_A	36084245	2776	0	0
g_div4.Div4Whole_A	36084245	3198	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939765	2843	0	0
T1	238413	0	0	0
T4	101693	0	0	0
T5	32953	0	0	0
T6	145738	0	0	0
T19	4032	2	0	0
T20	1376	0	0	0
T21	6218	9	0	0
T22	1523	0	0	0
T23	4275	0	0	0
T29	4135	3	0	0
T41	0	5	0	0
T79	0	4	0	0
T80	0	11	0	0
T114	0	11	0	0
T123	0	1	0	0
T124	0	6	0	0
T129	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939765	3364	0	0
T1	238413	0	0	0
T5	32953	0	0	0
T6	145738	0	0	0
T9	8074	1	0	0
T19	4032	2	0	0
T20	1376	0	0	0
T21	0	9	0	0
T26	2798	0	0	0
T27	8062	0	0	0
T28	2555	0	0	0
T29	4135	4	0	0
T41	0	5	0	0
T79	0	7	0	0
T80	0	10	0	0
T114	0	12	0	0
T123	0	1	0	0
T124	0	6	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36084245	2776	0	0
T1	119139	0	0	0
T4	25598	0	0	0
T5	16458	0	0	0
T6	72802	0	0	0
T19	2023	2	0	0
T20	663	0	0	0
T21	3677	9	0	0
T22	701	0	0	0
T23	2125	0	0	0
T29	2157	3	0	0
T41	0	5	0	0
T79	0	3	0	0
T80	0	11	0	0
T114	0	11	0	0
T123	0	1	0	0
T124	0	6	0	0
T129	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36084245	3198	0	0
T1	119139	0	0	0
T5	16458	0	0	0
T6	72802	0	0	0
T9	4003	1	0	0
T19	2023	2	0	0
T20	663	0	0	0
T21	0	9	0	0
T26	1339	0	0	0
T27	4019	0	0	0
T28	1231	0	0	0
T29	2157	4	0	0
T41	0	5	0	0
T79	0	4	0	0
T80	0	9	0	0
T114	0	12	0	0
T123	0	1	0	0
T124	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T26
1	0	Covered	T19,T21,T41
1	1	Covered	T9,T29,T19

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	73939765	2843	0	0
g_div2.Div2Whole_A	73939765	3364	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939765	2843	0	0
T1	238413	0	0	0
T4	101693	0	0	0
T5	32953	0	0	0
T6	145738	0	0	0
T19	4032	2	0	0
T20	1376	0	0	0
T21	6218	9	0	0
T22	1523	0	0	0
T23	4275	0	0	0
T29	4135	3	0	0
T41	0	5	0	0
T79	0	4	0	0
T80	0	11	0	0
T114	0	11	0	0
T123	0	1	0	0
T124	0	6	0	0
T129	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939765	3364	0	0
T1	238413	0	0	0
T5	32953	0	0	0
T6	145738	0	0	0
T9	8074	1	0	0
T19	4032	2	0	0
T20	1376	0	0	0
T21	0	9	0	0
T26	2798	0	0	0
T27	8062	0	0	0
T28	2555	0	0	0
T29	4135	4	0	0
T41	0	5	0	0
T79	0	7	0	0
T80	0	10	0	0
T114	0	12	0	0
T123	0	1	0	0
T124	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T26
1	0	Covered	T19,T21,T41
1	1	Covered	T9,T29,T19

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	36084245	2776	0	0
g_div4.Div4Whole_A	36084245	3198	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36084245	2776	0	0
T1	119139	0	0	0
T4	25598	0	0	0
T5	16458	0	0	0
T6	72802	0	0	0
T19	2023	2	0	0
T20	663	0	0	0
T21	3677	9	0	0
T22	701	0	0	0
T23	2125	0	0	0
T29	2157	3	0	0
T41	0	5	0	0
T79	0	3	0	0
T80	0	11	0	0
T114	0	11	0	0
T123	0	1	0	0
T124	0	6	0	0
T129	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36084245	3198	0	0
T1	119139	0	0	0
T5	16458	0	0	0
T6	72802	0	0	0
T9	4003	1	0	0
T19	2023	2	0	0
T20	663	0	0	0
T21	0	9	0	0
T26	1339	0	0	0
T27	4019	0	0	0
T28	1231	0	0	0
T29	2157	4	0	0
T41	0	5	0	0
T79	0	4	0	0
T80	0	9	0	0
T114	0	12	0	0
T123	0	1	0	0
T124	0	6	0	0