Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	108072924	427	0	0
StatusRise_A	108072924	427	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108072924	427	0	0
T1	201168	0	0	0
T4	197037	0	0	0
T5	25743	0	0	0
T6	523608	0	0	0
T19	3021	0	0	0
T20	4173	0	0	0
T21	4662	0	0	0
T22	4566	0	0	0
T23	0	10	0	0
T28	3711	5	0	0
T29	3099	0	0	0
T40	0	13	0	0
T161	0	5	0	0
T162	0	7	0	0
T163	0	12	0	0
T164	0	10	0	0
T165	0	2	0	0
T166	0	15	0	0
T167	0	4	0	0
T168	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108072924	427	0	0
T1	201168	0	0	0
T4	197037	0	0	0
T5	25743	0	0	0
T6	523608	0	0	0
T19	3021	0	0	0
T20	4173	0	0	0
T21	4662	0	0	0
T22	4566	0	0	0
T23	0	10	0	0
T28	3711	5	0	0
T29	3099	0	0	0
T40	0	13	0	0
T161	0	5	0	0
T162	0	7	0	0
T163	0	12	0	0
T164	0	10	0	0
T165	0	2	0	0
T166	0	15	0	0
T167	0	4	0	0
T168	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	36024308	138	0	0
StatusRise_A	36024308	138	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	138	0	0
T1	67056	0	0	0
T4	65679	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	0	3	0	0
T28	1237	2	0	0
T29	1033	0	0	0
T40	0	5	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	5	0	0
T164	0	3	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	138	0	0
T1	67056	0	0	0
T4	65679	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	0	3	0	0
T28	1237	2	0	0
T29	1033	0	0	0
T40	0	5	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	5	0	0
T164	0	3	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	36024308	140	0	0
StatusRise_A	36024308	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	140	0	0
T1	67056	0	0	0
T4	65679	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	0	3	0	0
T28	1237	1	0	0
T29	1033	0	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	140	0	0
T1	67056	0	0	0
T4	65679	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	0	3	0	0
T28	1237	1	0	0
T29	1033	0	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	3	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	36024308	149	0	0
StatusRise_A	36024308	149	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	149	0	0
T1	67056	0	0	0
T4	65679	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	0	4	0	0
T28	1237	2	0	0
T29	1033	0	0	0
T40	0	4	0	0
T161	0	1	0	0
T162	0	3	0	0
T163	0	3	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36024308	149	0	0
T1	67056	0	0	0
T4	65679	0	0	0
T5	8581	0	0	0
T6	174536	0	0	0
T19	1007	0	0	0
T20	1391	0	0	0
T21	1554	0	0	0
T22	1522	0	0	0
T23	0	4	0	0
T28	1237	2	0	0
T29	1033	0	0	0
T40	0	4	0	0
T161	0	1	0	0
T162	0	3	0	0
T163	0	3	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0