Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	856695994	30362	0	0
CgEnOn_A	856695994	21470	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856695994	30362	0	0
T1	2681918	3	0	0
T2	0	2	0	0
T4	428402	0	0	0
T5	370654	3	0	0
T6	1711316	3	0	0
T7	123197	7	0	0
T8	918967	153	0	0
T9	51758	3	0	0
T13	0	5	0	0
T15	0	5	0	0
T16	0	5	0	0
T17	0	5	0	0
T19	19504	0	0	0
T20	6585	0	0	0
T21	31472	0	0	0
T22	7206	0	0	0
T23	0	18	0	0
T26	17858	12	0	0
T27	51710	17	0	0
T28	27424	13	0	0
T29	46868	3	0	0
T30	0	5	0	0
T40	0	25	0	0
T42	0	1	0	0
T161	0	10	0	0
T162	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856695994	21470	0	0
T1	2681918	0	0	0
T2	0	49	0	0
T4	619338	0	0	0
T5	370654	0	0	0
T6	1711316	0	0	0
T7	80044	4	0	0
T8	598836	0	0	0
T9	33644	0	0	0
T12	0	10	0	0
T13	0	112	0	0
T14	0	11	0	0
T15	0	4	0	0
T16	0	5	0	0
T17	0	4	0	0
T19	28586	0	0	0
T20	9642	0	0	0
T21	46314	0	0	0
T22	10540	0	0	0
T23	0	27	0	0
T26	11656	0	0	0
T27	33592	0	0	0
T28	27424	10	0	0
T29	46868	0	0	0
T30	0	4	0	0
T40	0	37	0	0
T42	0	4	0	0
T43	0	8	0	0
T161	0	10	0	0
T162	0	10	0	0
T163	0	4	0	0
T164	0	3	0	0
T165	0	1	0	0
T169	0	14	0	0
T170	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36083857	160	0	0
CgEnOn_A	36083857	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36083857	160	0	0
T1	119139	0	0	0
T4	25597	0	0	0
T5	16458	0	0	0
T6	72802	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	2023	0	0	0
T20	662	0	0	0
T21	3677	0	0	0
T22	701	0	0	0
T23	0	3	0	0
T28	1231	1	0	0
T29	2156	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36083857	160	0	0
T1	119139	0	0	0
T4	25597	0	0	0
T5	16458	0	0	0
T6	72802	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	2023	0	0	0
T20	662	0	0	0
T21	3677	0	0	0
T22	701	0	0	0
T23	0	3	0	0
T28	1231	1	0	0
T29	2156	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18041556	160	0	0
CgEnOn_A	18041556	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041556	160	0	0
T1	59569	0	0	0
T4	12799	0	0	0
T5	8229	0	0	0
T6	36401	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	1011	0	0	0
T20	331	0	0	0
T21	1838	0	0	0
T22	350	0	0	0
T23	0	3	0	0
T28	615	1	0	0
T29	1078	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041556	160	0	0
T1	59569	0	0	0
T4	12799	0	0	0
T5	8229	0	0	0
T6	36401	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	1011	0	0	0
T20	331	0	0	0
T21	1838	0	0	0
T22	350	0	0	0
T23	0	3	0	0
T28	615	1	0	0
T29	1078	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18041556	160	0	0
CgEnOn_A	18041556	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041556	160	0	0
T1	59569	0	0	0
T4	12799	0	0	0
T5	8229	0	0	0
T6	36401	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	1011	0	0	0
T20	331	0	0	0
T21	1838	0	0	0
T22	350	0	0	0
T23	0	3	0	0
T28	615	1	0	0
T29	1078	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041556	160	0	0
T1	59569	0	0	0
T4	12799	0	0	0
T5	8229	0	0	0
T6	36401	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	1011	0	0	0
T20	331	0	0	0
T21	1838	0	0	0
T22	350	0	0	0
T23	0	3	0	0
T28	615	1	0	0
T29	1078	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18041556	160	0	0
CgEnOn_A	18041556	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041556	160	0	0
T1	59569	0	0	0
T4	12799	0	0	0
T5	8229	0	0	0
T6	36401	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	1011	0	0	0
T20	331	0	0	0
T21	1838	0	0	0
T22	350	0	0	0
T23	0	3	0	0
T28	615	1	0	0
T29	1078	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041556	160	0	0
T1	59569	0	0	0
T4	12799	0	0	0
T5	8229	0	0	0
T6	36401	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	1011	0	0	0
T20	331	0	0	0
T21	1838	0	0	0
T22	350	0	0	0
T23	0	3	0	0
T28	615	1	0	0
T29	1078	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	73939315	160	0	0
CgEnOn_A	73939315	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939315	160	0	0
T1	238412	0	0	0
T4	101692	0	0	0
T5	32953	0	0	0
T6	145737	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	4032	0	0	0
T20	1376	0	0	0
T21	6218	0	0	0
T22	1522	0	0	0
T23	0	3	0	0
T28	2554	1	0	0
T29	4134	0	0	0
T30	0	1	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939315	143	0	0
T1	238412	0	0	0
T4	101692	0	0	0
T5	32953	0	0	0
T6	145737	0	0	0
T13	0	1	0	0
T16	0	1	0	0
T19	4032	0	0	0
T20	1376	0	0	0
T21	6218	0	0	0
T22	1522	0	0	0
T23	0	3	0	0
T28	2554	1	0	0
T29	4134	0	0	0
T40	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	4	0	0
T164	0	3	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81077742	151	0	0
CgEnOn_A	81077742	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	151	0	0
T1	248353	0	0	0
T4	105934	0	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T13	0	1	0	0
T19	4200	0	0	0
T20	1433	0	0	0
T21	6477	0	0	0
T22	1586	0	0	0
T23	0	3	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	5	0	0
T164	0	3	0	0
T166	0	4	0	0
T167	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	142	0	0
T1	248353	0	0	0
T4	105934	0	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T19	4200	0	0	0
T20	1433	0	0	0
T21	6477	0	0	0
T22	1586	0	0	0
T23	0	3	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	5	0	0
T164	0	3	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81077742	151	0	0
CgEnOn_A	81077742	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	151	0	0
T1	248353	0	0	0
T4	105934	0	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T13	0	1	0	0
T19	4200	0	0	0
T20	1433	0	0	0
T21	6477	0	0	0
T22	1586	0	0	0
T23	0	3	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	5	0	0
T164	0	3	0	0
T166	0	4	0	0
T167	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	142	0	0
T1	248353	0	0	0
T4	105934	0	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T19	4200	0	0	0
T20	1433	0	0	0
T21	6477	0	0	0
T22	1586	0	0	0
T23	0	3	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	5	0	0
T164	0	3	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39008487	159	0	0
CgEnOn_A	39008487	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39008487	159	0	0
T1	119211	0	0	0
T4	50848	0	0	0
T5	16477	0	0	0
T6	72872	0	0	0
T17	0	1	0	0
T19	2016	0	0	0
T20	688	0	0	0
T21	3109	0	0	0
T22	761	0	0	0
T23	0	4	0	0
T28	1185	2	0	0
T29	2067	0	0	0
T40	0	4	0	0
T71	0	1	0	0
T72	0	1	0	0
T161	0	1	0	0
T162	0	3	0	0
T163	0	3	0	0
T164	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39008487	152	0	0
T1	119211	0	0	0
T4	50848	0	0	0
T5	16477	0	0	0
T6	72872	0	0	0
T17	0	1	0	0
T19	2016	0	0	0
T20	688	0	0	0
T21	3109	0	0	0
T22	761	0	0	0
T23	0	4	0	0
T28	1185	2	0	0
T29	2067	0	0	0
T40	0	4	0	0
T161	0	1	0	0
T162	0	3	0	0
T163	0	3	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T23,T40
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18041556	4892	0	0
CgEnOn_A	18041556	2697	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041556	4892	0	0
T1	59569	1	0	0
T5	8229	1	0	0
T6	36401	1	0	0
T7	4779	1	0	0
T8	34855	51	0	0
T9	2001	1	0	0
T26	669	1	0	0
T27	2009	1	0	0
T28	615	2	0	0
T29	1078	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18041556	2697	0	0
T1	59569	0	0	0
T2	0	16	0	0
T4	12799	0	0	0
T5	8229	0	0	0
T6	36401	0	0	0
T12	0	3	0	0
T13	0	37	0	0
T14	0	11	0	0
T19	1011	0	0	0
T20	331	0	0	0
T21	1838	0	0	0
T22	350	0	0	0
T23	0	3	0	0
T28	615	1	0	0
T29	1078	0	0	0
T40	0	4	0	0
T42	0	1	0	0
T169	0	4	0	0
T170	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T23,T40
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36083857	4904	0	0
CgEnOn_A	36083857	2709	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36083857	4904	0	0
T1	119139	1	0	0
T5	16458	1	0	0
T6	72802	1	0	0
T7	9558	1	0	0
T8	69699	51	0	0
T9	4002	1	0	0
T26	1338	1	0	0
T27	4018	1	0	0
T28	1231	2	0	0
T29	2156	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36083857	2709	0	0
T1	119139	0	0	0
T2	0	17	0	0
T4	25597	0	0	0
T5	16458	0	0	0
T6	72802	0	0	0
T12	0	3	0	0
T13	0	38	0	0
T19	2023	0	0	0
T20	662	0	0	0
T21	3677	0	0	0
T22	701	0	0	0
T23	0	3	0	0
T28	1231	1	0	0
T29	2156	0	0	0
T40	0	4	0	0
T42	0	1	0	0
T43	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T23,T40
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	73939315	4931	0	0
CgEnOn_A	73939315	2719	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939315	4931	0	0
T1	238412	1	0	0
T5	32953	1	0	0
T6	145737	1	0	0
T7	19210	1	0	0
T8	143716	51	0	0
T9	8074	1	0	0
T26	2797	1	0	0
T27	8061	1	0	0
T28	2554	2	0	0
T29	4134	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73939315	2719	0	0
T1	238412	0	0	0
T2	0	14	0	0
T4	101692	0	0	0
T5	32953	0	0	0
T6	145737	0	0	0
T12	0	4	0	0
T13	0	32	0	0
T19	4032	0	0	0
T20	1376	0	0	0
T21	6218	0	0	0
T22	1522	0	0	0
T23	0	3	0	0
T28	2554	1	0	0
T29	4134	0	0	0
T40	0	4	0	0
T42	0	1	0	0
T43	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T23,T40
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39008487	4931	0	0
CgEnOn_A	39008487	2719	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39008487	4931	0	0
T1	119211	1	0	0
T5	16477	1	0	0
T6	72872	1	0	0
T7	9606	1	0	0
T8	71861	51	0	0
T9	4037	1	0	0
T26	1398	1	0	0
T27	4030	1	0	0
T28	1185	3	0	0
T29	2067	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39008487	2719	0	0
T1	119211	0	0	0
T2	0	18	0	0
T4	50848	0	0	0
T5	16477	0	0	0
T6	72872	0	0	0
T12	0	4	0	0
T13	0	34	0	0
T19	2016	0	0	0
T20	688	0	0	0
T21	3109	0	0	0
T22	761	0	0	0
T23	0	4	0	0
T28	1185	2	0	0
T29	2067	0	0	0
T40	0	4	0	0
T42	0	1	0	0
T43	0	1	0	0
T169	0	4	0	0
T170	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Covered	T7,T26,T27
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81077742	2396	0	0
CgEnOn_A	81077742	2387	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	2396	0	0
T1	248353	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T7	20011	4	0	0
T8	149709	0	0	0
T9	8411	0	0	0
T23	0	3	0	0
T26	2914	9	0	0
T27	8398	14	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T42	0	1	0	0
T43	0	6	0	0
T127	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	2387	0	0
T1	248353	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T7	20011	4	0	0
T8	149709	0	0	0
T9	8411	0	0	0
T23	0	3	0	0
T26	2914	9	0	0
T27	8398	14	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T42	0	1	0	0
T43	0	6	0	0
T127	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Covered	T7,T26,T27
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81077742	2341	0	0
CgEnOn_A	81077742	2332	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	2341	0	0
T1	248353	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T7	20011	6	0	0
T8	149709	0	0	0
T9	8411	0	0	0
T23	0	3	0	0
T26	2914	10	0	0
T27	8398	10	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T42	0	1	0	0
T43	0	4	0	0
T127	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	2332	0	0
T1	248353	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T7	20011	6	0	0
T8	149709	0	0	0
T9	8411	0	0	0
T23	0	3	0	0
T26	2914	10	0	0
T27	8398	10	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T42	0	1	0	0
T43	0	4	0	0
T127	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Covered	T7,T26,T27
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81077742	2363	0	0
CgEnOn_A	81077742	2354	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	2363	0	0
T1	248353	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T7	20011	4	0	0
T8	149709	0	0	0
T9	8411	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T26	2914	11	0	0
T27	8398	7	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T42	0	1	0	0
T127	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	2354	0	0
T1	248353	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T7	20011	4	0	0
T8	149709	0	0	0
T9	8411	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T26	2914	11	0	0
T27	8398	7	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T42	0	1	0	0
T127	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T28,T4
1	0	Covered	T7,T26,T27
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81077742	2343	0	0
CgEnOn_A	81077742	2334	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	2343	0	0
T1	248353	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T7	20011	5	0	0
T8	149709	0	0	0
T9	8411	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T26	2914	6	0	0
T27	8398	10	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T42	0	1	0	0
T127	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81077742	2334	0	0
T1	248353	0	0	0
T2	0	2	0	0
T5	34327	0	0	0
T6	163815	0	0	0
T7	20011	5	0	0
T8	149709	0	0	0
T9	8411	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T26	2914	6	0	0
T27	8398	10	0	0
T28	2504	2	0	0
T29	4307	0	0	0
T40	0	5	0	0
T42	0	1	0	0
T127	0	9	0	0