Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	216007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

478934

1

T5

889

T8

18

T9

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	201125	1			T5	389		T8	18		T9	16
values[0x0]	234654	1			T5	367		T8	17		T9	13
values[0x1]	259162	1			T5	434		T8	20		T9	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150913	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

544028

1

T5

967

T8

23

T9

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2598	1			T5	3		T21	1		T4	1
valid_sources[0x01]	2387	1			T5	2		T9	5		T30	1
valid_sources[0x02]	3447	1			T5	9		T30	1		T32	3
valid_sources[0x03]	3235	1			T5	6		T32	2		T21	2
valid_sources[0x04]	3233	1			T5	3		T84	4		T39	1
valid_sources[0x05]	2524	1			T5	9		T28	1		T21	2
valid_sources[0x06]	2150	1			T5	5		T27	13		T32	7
valid_sources[0x07]	2626	1			T5	7		T8	2		T84	2
valid_sources[0x08]	2678	1			T5	5		T27	3		T32	2
valid_sources[0x09]	2046	1			T5	4		T26	1		T30	1
valid_sources[0x0a]	2673	1			T5	5		T26	1		T30	1
valid_sources[0x0b]	2090	1			T5	5		T27	1		T21	3
valid_sources[0x0c]	2457	1			T5	6		T32	2		T41	1
valid_sources[0x0d]	2251	1			T5	4		T28	2		T32	1
valid_sources[0x0e]	2408	1			T5	3		T26	2		T30	1
valid_sources[0x0f]	3407	1			T5	7		T32	145		T20	1
valid_sources[0x10]	2663	1			T5	5		T9	1		T30	1
valid_sources[0x11]	2936	1			T5	2		T32	11		T21	1
valid_sources[0x12]	2753	1			T26	1		T27	2		T84	2
valid_sources[0x13]	2532	1			T5	10		T30	2		T4	1
valid_sources[0x14]	2342	1			T5	8		T32	3		T21	1
valid_sources[0x15]	2599	1			T5	3		T30	2		T23	1
valid_sources[0x16]	2214	1			T5	4		T30	1		T84	2
valid_sources[0x17]	2491	1			T5	3		T26	1		T28	1
valid_sources[0x18]	2403	1			T5	5		T28	2		T32	1
valid_sources[0x19]	2903	1			T5	4		T36	1		T3	1
valid_sources[0x1a]	2231	1			T5	6		T28	1		T32	129
valid_sources[0x1b]	1942	1			T5	3		T32	6		T21	1
valid_sources[0x1c]	5126	1			T5	6		T30	1		T20	1
valid_sources[0x1d]	4486	1			T5	3		T32	232		T36	1
valid_sources[0x1e]	2312	1			T5	6		T41	1		T21	6
valid_sources[0x1f]	2689	1			T5	4		T4	1		T3	3
valid_sources[0x20]	3046	1			T5	7		T26	1		T32	2
valid_sources[0x21]	2807	1			T5	7		T32	1		T39	2
valid_sources[0x22]	2689	1			T5	5		T28	1		T32	92
valid_sources[0x23]	2624	1			T5	4		T9	9		T30	1
valid_sources[0x24]	2162	1			T5	8		T32	1		T21	1
valid_sources[0x25]	2085	1			T5	4		T30	1		T77	3
valid_sources[0x26]	3411	1			T5	8		T8	9		T27	1
valid_sources[0x27]	2480	1			T5	5		T30	1		T83	1
valid_sources[0x28]	3021	1			T5	3		T28	1		T84	5
valid_sources[0x29]	2346	1			T5	3		T30	2		T32	3
valid_sources[0x2a]	3836	1			T5	4		T8	1		T84	1
valid_sources[0x2b]	2584	1			T5	2		T28	1		T32	132
valid_sources[0x2c]	2973	1			T5	5		T28	1		T21	3
valid_sources[0x2d]	2846	1			T27	2		T31	3		T32	9
valid_sources[0x2e]	2628	1			T5	3		T32	157		T39	1
valid_sources[0x2f]	2410	1			T5	4		T21	1		T24	1
valid_sources[0x30]	2453	1			T5	3		T20	1		T4	4
valid_sources[0x31]	2739	1			T5	6		T28	1		T41	1
valid_sources[0x32]	3090	1			T5	3		T9	1		T30	1
valid_sources[0x33]	2591	1			T5	5		T26	1		T84	1
valid_sources[0x34]	2500	1			T5	4		T83	2		T32	3
valid_sources[0x35]	2480	1			T5	5		T26	1		T84	3
valid_sources[0x36]	2685	1			T5	3		T27	5		T30	1
valid_sources[0x37]	2882	1			T5	8		T30	1		T21	1
valid_sources[0x38]	2218	1			T5	6		T26	1		T32	3
valid_sources[0x39]	3526	1			T5	4		T8	1		T30	1
valid_sources[0x3a]	3219	1			T5	6		T28	1		T32	1
valid_sources[0x3b]	2663	1			T5	6		T26	2		T32	1
valid_sources[0x3c]	2382	1			T5	2		T36	1		T20	1
valid_sources[0x3d]	2797	1			T5	1		T84	1		T32	4
valid_sources[0x3e]	2574	1			T5	3		T27	3		T20	1
valid_sources[0x3f]	4629	1			T5	9		T32	7		T20	1
valid_sources[0x40]	2404	1			T5	7		T41	2		T21	4
valid_sources[0x41]	2697	1			T5	2		T8	2		T28	1
valid_sources[0x42]	2451	1			T5	3		T22	1		T4	2
valid_sources[0x43]	2248	1			T5	1		T8	4		T84	1
valid_sources[0x44]	3103	1			T5	3		T28	4		T21	2
valid_sources[0x45]	2834	1			T5	3		T84	3		T32	5
valid_sources[0x46]	2856	1			T5	10		T8	2		T32	131
valid_sources[0x47]	2245	1			T5	8		T28	1		T32	7
valid_sources[0x48]	2844	1			T5	2		T32	2		T21	4
valid_sources[0x49]	2983	1			T5	1		T28	1		T30	1
valid_sources[0x4a]	2322	1			T5	8		T26	2		T28	1
valid_sources[0x4b]	3139	1			T5	3		T1	17		T21	4
valid_sources[0x4c]	2493	1			T5	2		T28	1		T32	3
valid_sources[0x4d]	2867	1			T5	3		T8	3		T32	142
valid_sources[0x4e]	2671	1			T5	3		T30	1		T39	1
valid_sources[0x4f]	2342	1			T5	13		T27	4		T28	1
valid_sources[0x50]	2345	1			T5	4		T30	1		T12	2
valid_sources[0x51]	5642	1			T5	5		T28	1		T20	1
valid_sources[0x52]	3132	1			T5	5		T32	4		T21	3
valid_sources[0x53]	2117	1			T5	3		T28	1		T32	1
valid_sources[0x54]	2895	1			T5	1		T27	3		T32	4
valid_sources[0x55]	2370	1			T5	5		T30	1		T32	3
valid_sources[0x56]	2016	1			T5	3		T21	1		T23	1
valid_sources[0x57]	2182	1			T5	6		T21	1		T23	3
valid_sources[0x58]	2248	1			T5	4		T8	4		T21	1
valid_sources[0x59]	2987	1			T5	8		T27	4		T32	79
valid_sources[0x5a]	2351	1			T5	7		T32	1		T36	1
valid_sources[0x5b]	2817	1			T5	4		T9	1		T32	4
valid_sources[0x5c]	5527	1			T5	7		T32	2		T21	1
valid_sources[0x5d]	2161	1			T5	3		T83	1		T48	1
valid_sources[0x5e]	2877	1			T5	4		T9	3		T4	1
valid_sources[0x5f]	5145	1			T5	4		T30	1		T6	1939
valid_sources[0x60]	2009	1			T5	3		T9	1		T30	1
valid_sources[0x61]	2592	1			T5	4		T32	15		T41	1
valid_sources[0x62]	2383	1			T5	4		T30	1		T36	1
valid_sources[0x63]	2512	1			T5	3		T32	1		T21	3
valid_sources[0x64]	2513	1			T5	7		T32	1		T97	1
valid_sources[0x65]	2499	1			T5	4		T32	3		T41	1
valid_sources[0x66]	2884	1			T5	8		T28	1		T32	166
valid_sources[0x67]	2086	1			T5	4		T20	2		T21	3
valid_sources[0x68]	3061	1			T5	2		T84	11		T36	1
valid_sources[0x69]	4047	1			T5	5		T83	7		T36	1
valid_sources[0x6a]	2435	1			T5	9		T9	2		T26	1
valid_sources[0x6b]	2699	1			T5	5		T9	7		T28	1
valid_sources[0x6c]	2465	1			T5	8		T32	6		T36	1
valid_sources[0x6d]	2674	1			T5	3		T30	1		T190	5
valid_sources[0x6e]	2403	1			T5	4		T32	134		T36	1
valid_sources[0x6f]	2949	1			T5	3		T39	1		T41	1
valid_sources[0x70]	2934	1			T5	4		T30	1		T32	4
valid_sources[0x71]	2238	1			T84	3		T23	1		T3	2
valid_sources[0x72]	3117	1			T5	6		T32	278		T21	4
valid_sources[0x73]	2374	1			T5	6		T36	1		T41	1
valid_sources[0x74]	2633	1			T5	3		T21	1		T4	1
valid_sources[0x75]	3293	1			T5	1		T32	110		T36	1
valid_sources[0x76]	2170	1			T5	4		T28	1		T20	2
valid_sources[0x77]	2731	1			T5	2		T8	4		T32	8
valid_sources[0x78]	2949	1			T5	6		T32	80		T20	1
valid_sources[0x79]	2283	1			T5	5		T8	2		T28	2
valid_sources[0x7a]	2464	1			T5	4		T32	281		T41	1
valid_sources[0x7b]	2213	1			T5	3		T28	1		T41	1
valid_sources[0x7c]	2740	1			T5	2		T30	2		T32	1
valid_sources[0x7d]	2625	1			T5	7		T28	1		T32	2
valid_sources[0x7e]	2788	1			T5	4		T36	2		T1	54
valid_sources[0x7f]	2111	1			T5	2		T32	128		T4	1
valid_sources[0x80]	2514	1			T5	2		T30	1		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

133768

1

T5

259

T8

8

T9

7

values[0x0]

all_enables

biggest_size

186169

1

T5

317

T8

6

T9

4

values[0x1]

all_enables

biggest_size

158997

1

T5

313

T8

4

T9

3