Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T28
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T28
1	0	Covered	T51,T52,T53
1	1	Covered	T5,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	199618227	8250	0	0
GateOpen_A	199618227	14668	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199618227	8250	0	0
T5	44986	27	0	0
T6	1292700	39	0	0
T8	17314	0	0	0
T9	4895	0	0	0
T25	0	4	0	0
T26	11842	0	0	0
T27	8278	4	0	0
T28	4708	4	0	0
T29	19720	0	0	0
T30	4289	3	0	0
T31	8098	4	0	0
T32	0	137	0	0
T39	0	16	0	0
T51	0	4	0	0
T180	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199618227	14668	0	0
T5	44986	35	0	0
T6	1292700	55	0	0
T7	0	12	0	0
T8	17314	4	0	0
T9	4895	0	0	0
T26	11842	0	0	0
T27	8278	8	0	0
T28	4708	4	0	0
T29	19720	4	0	0
T30	4289	3	0	0
T31	8098	8	0	0
T32	0	35	0	0
T83	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T28
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T28
1	0	Covered	T51,T52,T53
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	21599985	1998	0	0
GateOpen_A	21599985	3601	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599985	1998	0	0
T5	4446	5	0	0
T6	141141	8	0	0
T8	2015	0	0	0
T9	574	0	0	0
T25	0	1	0	0
T26	1358	0	0	0
T27	907	1	0	0
T28	517	1	0	0
T29	2343	0	0	0
T30	473	0	0	0
T31	880	1	0	0
T32	0	32	0	0
T39	0	4	0	0
T51	0	1	0	0
T180	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599985	3601	0	0
T5	4446	7	0	0
T6	141141	12	0	0
T7	0	3	0	0
T8	2015	1	0	0
T9	574	0	0	0
T26	1358	0	0	0
T27	907	2	0	0
T28	517	1	0	0
T29	2343	1	0	0
T30	473	0	0	0
T31	880	2	0	0
T32	0	35	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T28
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T28
1	0	Covered	T51,T52,T53
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	43200432	2117	0	0
GateOpen_A	43200432	3720	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200432	2117	0	0
T5	8894	7	0	0
T6	282298	10	0	0
T8	4032	0	0	0
T9	1148	0	0	0
T25	0	1	0	0
T26	2718	0	0	0
T27	1813	1	0	0
T28	1034	1	0	0
T29	4688	0	0	0
T30	945	1	0	0
T31	1759	1	0	0
T32	0	38	0	0
T39	0	4	0	0
T51	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200432	3720	0	0
T5	8894	9	0	0
T6	282298	14	0	0
T7	0	3	0	0
T8	4032	1	0	0
T9	1148	0	0	0
T26	2718	0	0	0
T27	1813	2	0	0
T28	1034	1	0	0
T29	4688	1	0	0
T30	945	1	0	0
T31	1759	2	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T28
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T28
1	0	Covered	T51,T52,T53
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	88028839	2078	0	0
GateOpen_A	88028839	3684	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028839	2078	0	0
T5	19850	9	0	0
T6	564138	10	0	0
T8	7511	0	0	0
T9	2115	0	0	0
T25	0	1	0	0
T26	5177	0	0	0
T27	3705	1	0	0
T28	2105	1	0	0
T29	8459	0	0	0
T30	1914	1	0	0
T31	3639	1	0	0
T32	0	33	0	0
T39	0	5	0	0
T51	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028839	3684	0	0
T5	19850	11	0	0
T6	564138	14	0	0
T7	0	3	0	0
T8	7511	1	0	0
T9	2115	0	0	0
T26	5177	0	0	0
T27	3705	2	0	0
T28	2105	1	0	0
T29	8459	1	0	0
T30	1914	1	0	0
T31	3639	2	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T28
0	1	Covered	T5,T6,T31
1	0	Covered	T5,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T28
1	0	Covered	T51,T52,T53
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	46788971	2057	0	0
GateOpen_A	46788971	3663	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46788971	2057	0	0
T5	11796	6	0	0
T6	305123	11	0	0
T8	3756	0	0	0
T9	1058	0	0	0
T25	0	1	0	0
T26	2589	0	0	0
T27	1853	1	0	0
T28	1052	1	0	0
T29	4230	0	0	0
T30	957	1	0	0
T31	1820	1	0	0
T32	0	34	0	0
T39	0	3	0	0
T51	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46788971	3663	0	0
T5	11796	8	0	0
T6	305123	15	0	0
T7	0	3	0	0
T8	3756	1	0	0
T9	1058	0	0	0
T26	2589	0	0	0
T27	1853	2	0	0
T28	1052	1	0	0
T29	4230	1	0	0
T30	957	1	0	0
T31	1820	2	0	0
T83	0	1	0	0