Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	196928480	32894	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196928480	32894	0	0
T1	64440	37	0	0
T2	939220	330	0	0
T3	0	130	0	0
T4	83735	0	0	0
T12	0	69	0	0
T13	0	555	0	0
T14	0	192	0	0
T15	0	392	0	0
T16	0	45	0	0
T17	0	183	0	0
T18	0	55	0	0
T19	42530	0	0	0
T20	11665	0	0	0
T21	907655	0	0	0
T22	8330	0	0	0
T23	790270	0	0	0
T24	9990	0	0	0
T25	6210	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39385696	4987	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	4987	0	0
T1	12888	7	0	0
T2	187844	43	0	0
T3	0	19	0	0
T4	16747	0	0	0
T12	0	10	0	0
T13	0	98	0	0
T14	0	28	0	0
T15	0	52	0	0
T16	0	7	0	0
T17	0	34	0	0
T18	0	9	0	0
T19	8506	0	0	0
T20	2333	0	0	0
T21	181531	0	0	0
T22	1666	0	0	0
T23	158054	0	0	0
T24	1998	0	0	0
T25	1242	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39385696	4904	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	4904	0	0
T1	12888	7	0	0
T2	187844	48	0	0
T3	0	19	0	0
T4	16747	0	0	0
T12	0	9	0	0
T13	0	98	0	0
T14	0	28	0	0
T15	0	50	0	0
T16	0	7	0	0
T17	0	34	0	0
T18	0	9	0	0
T19	8506	0	0	0
T20	2333	0	0	0
T21	181531	0	0	0
T22	1666	0	0	0
T23	158054	0	0	0
T24	1998	0	0	0
T25	1242	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39385696	6622	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	6622	0	0
T1	12888	7	0	0
T2	187844	65	0	0
T3	0	26	0	0
T4	16747	0	0	0
T12	0	14	0	0
T13	0	109	0	0
T14	0	37	0	0
T15	0	81	0	0
T16	0	9	0	0
T17	0	35	0	0
T18	0	11	0	0
T19	8506	0	0	0
T20	2333	0	0	0
T21	181531	0	0	0
T22	1666	0	0	0
T23	158054	0	0	0
T24	1998	0	0	0
T25	1242	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39385696	6600	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	6600	0	0
T1	12888	7	0	0
T2	187844	65	0	0
T3	0	27	0	0
T4	16747	0	0	0
T12	0	13	0	0
T13	0	112	0	0
T14	0	40	0	0
T15	0	79	0	0
T16	0	10	0	0
T17	0	35	0	0
T18	0	11	0	0
T19	8506	0	0	0
T20	2333	0	0	0
T21	181531	0	0	0
T22	1666	0	0	0
T23	158054	0	0	0
T24	1998	0	0	0
T25	1242	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39385696	9781	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	9781	0	0
T1	12888	9	0	0
T2	187844	109	0	0
T3	0	39	0	0
T4	16747	0	0	0
T12	0	23	0	0
T13	0	138	0	0
T14	0	59	0	0
T15	0	130	0	0
T16	0	12	0	0
T17	0	45	0	0
T18	0	15	0	0
T19	8506	0	0	0
T20	2333	0	0	0
T21	181531	0	0	0
T22	1666	0	0	0
T23	158054	0	0	0
T24	1998	0	0	0
T25	1242	0	0	0