Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	39385696	36870603	0	0
AllClkBypReqTrue_A	39385696	88898	0	0
IoClkBypReqFalse_A	39385696	36813284	0	2415
IoClkBypReqTrue_A	39385696	141585	0	0
LcClkBypAckFalse_A	39385696	36877633	0	0
LcClkBypAckTrue_A	39385696	81868	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	36870603	0	0
T5	11796	6009	0	0
T6	713661	710266	0	0
T8	1955	1761	0	0
T9	2202	1798	0	0
T26	1401	1233	0	0
T27	1853	1784	0	0
T28	2127	2045	0	0
T29	2202	1993	0	0
T30	1714	1580	0	0
T31	947	886	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	88898	0	0
T5	11796	144	0	0
T6	713661	1275	0	0
T7	0	173	0	0
T8	1955	162	0	0
T9	2202	234	0	0
T26	1401	109	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	177	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	343	0	0
T77	0	164	0	0
T83	0	120	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	36813284	0	2415
T5	11796	5945	0	3
T6	713661	709315	0	3
T8	1955	1896	0	3
T9	2202	1618	0	3
T26	1401	1186	0	3
T27	1853	1782	0	3
T28	2127	2043	0	3
T29	2202	1698	0	3
T30	1714	1578	0	3
T31	947	884	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	141585	0	0
T5	11796	196	0	0
T6	713661	2204	0	0
T7	0	275	0	0
T8	1955	25	0	0
T9	2202	412	0	0
T26	1401	154	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	470	0	0
T30	1714	0	0	0
T31	947	0	0	0
T77	0	235	0	0
T82	0	28	0	0
T83	0	197	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	36877633	0	0
T5	11796	6053	0	0
T6	713661	710285	0	0
T8	1955	1903	0	0
T9	2202	1831	0	0
T26	1401	1275	0	0
T27	1853	1784	0	0
T28	2127	2045	0	0
T29	2202	1942	0	0
T30	1714	1580	0	0
T31	947	886	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	81868	0	0
T5	11796	100	0	0
T6	713661	1256	0	0
T7	0	204	0	0
T8	1955	20	0	0
T9	2202	201	0	0
T26	1401	67	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	228	0	0
T30	1714	0	0	0
T31	947	0	0	0
T77	0	92	0	0
T82	0	17	0	0
T83	0	145	0	0