Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	390824792	9952	0	0
TransStop_A	390824792	5183	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390824792	9952	0	0
T5	98296	8	0	0
T6	2542648	81	0	0
T7	0	48	0	0
T8	31300	0	0	0
T9	8812	0	0	0
T20	0	21	0	0
T26	21572	0	0	0
T27	15436	4	0	0
T28	8772	4	0	0
T29	35248	0	0	0
T30	7976	4	0	0
T31	15160	0	0	0
T32	0	65	0	0
T38	0	16	0	0
T84	0	19	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390824792	5183	0	0
T6	2542648	40	0	0
T7	0	29	0	0
T20	0	6	0	0
T24	0	16	0	0
T27	15436	4	0	0
T28	8772	4	0	0
T29	35248	0	0	0
T30	7976	4	0	0
T31	15160	0	0	0
T32	0	28	0	0
T38	0	12	0	0
T48	22112	0	0	0
T77	8200	0	0	0
T82	4604	0	0	0
T83	12224	0	0	0
T84	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	97706198	2538	0	0
TransStop_A	97706198	1327	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97706198	2538	0	0
T5	24574	2	0	0
T6	635662	23	0	0
T7	0	13	0	0
T8	7825	0	0	0
T9	2203	0	0	0
T20	0	4	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2193	1	0	0
T29	8812	0	0	0
T30	1994	1	0	0
T31	3790	0	0	0
T32	0	20	0	0
T38	0	5	0	0
T84	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97706198	1327	0	0
T6	635662	10	0	0
T7	0	6	0	0
T20	0	1	0	0
T24	0	3	0	0
T27	3859	1	0	0
T28	2193	1	0	0
T29	8812	0	0	0
T30	1994	1	0	0
T31	3790	0	0	0
T32	0	9	0	0
T38	0	3	0	0
T48	5528	0	0	0
T77	2050	0	0	0
T82	1151	0	0	0
T83	3056	0	0	0
T84	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	97706198	2450	0	0
TransStop_A	97706198	1256	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97706198	2450	0	0
T5	24574	2	0	0
T6	635662	16	0	0
T7	0	12	0	0
T8	7825	0	0	0
T9	2203	0	0	0
T20	0	5	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2193	1	0	0
T29	8812	0	0	0
T30	1994	1	0	0
T31	3790	0	0	0
T32	0	12	0	0
T38	0	4	0	0
T84	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97706198	1256	0	0
T6	635662	9	0	0
T7	0	9	0	0
T20	0	1	0	0
T24	0	5	0	0
T27	3859	1	0	0
T28	2193	1	0	0
T29	8812	0	0	0
T30	1994	1	0	0
T31	3790	0	0	0
T32	0	5	0	0
T38	0	3	0	0
T48	5528	0	0	0
T77	2050	0	0	0
T82	1151	0	0	0
T83	3056	0	0	0
T84	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	97706198	2504	0	0
TransStop_A	97706198	1315	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97706198	2504	0	0
T5	24574	2	0	0
T6	635662	15	0	0
T7	0	11	0	0
T8	7825	0	0	0
T9	2203	0	0	0
T20	0	7	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2193	1	0	0
T29	8812	0	0	0
T30	1994	1	0	0
T31	3790	0	0	0
T32	0	18	0	0
T38	0	4	0	0
T84	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97706198	1315	0	0
T6	635662	7	0	0
T7	0	7	0	0
T20	0	2	0	0
T24	0	4	0	0
T27	3859	1	0	0
T28	2193	1	0	0
T29	8812	0	0	0
T30	1994	1	0	0
T31	3790	0	0	0
T32	0	8	0	0
T38	0	4	0	0
T48	5528	0	0	0
T77	2050	0	0	0
T82	1151	0	0	0
T83	3056	0	0	0
T84	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	97706198	2460	0	0
TransStop_A	97706198	1285	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97706198	2460	0	0
T5	24574	2	0	0
T6	635662	27	0	0
T7	0	12	0	0
T8	7825	0	0	0
T9	2203	0	0	0
T20	0	5	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2193	1	0	0
T29	8812	0	0	0
T30	1994	1	0	0
T31	3790	0	0	0
T32	0	15	0	0
T38	0	3	0	0
T84	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97706198	1285	0	0
T6	635662	14	0	0
T7	0	7	0	0
T20	0	2	0	0
T24	0	4	0	0
T27	3859	1	0	0
T28	2193	1	0	0
T29	8812	0	0	0
T30	1994	1	0	0
T31	3790	0	0	0
T32	0	6	0	0
T38	0	2	0	0
T48	5528	0	0	0
T77	2050	0	0	0
T82	1151	0	0	0
T83	3056	0	0	0
T84	0	1	0	0