Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	39385696	2898891	0	62

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	2898891	0	62
T1	12888	2023	0	1
T2	187844	37310	0	1
T3	0	12641	0	1
T4	16747	0	0	0
T12	0	7979	0	1
T13	0	25451	0	0
T14	0	16506	0	1
T15	0	41998	0	0
T16	0	6222	0	0
T17	0	0	0	1
T18	0	0	0	1
T19	8506	0	0	0
T20	2333	0	0	0
T21	181531	0	0	0
T22	1666	0	0	0
T23	158054	0	0	0
T24	1998	0	0	0
T25	1242	0	0	0
T33	0	666	0	1
T34	0	603	0	1
T118	0	0	0	1