Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	40346326	498746	0	0
clk_enables_rd_A	40346326	9794	0	0
clk_hints_rd_A	40346326	9128	0	0
extclk_ctrl_rd_A	40346326	11864	0	0
extclk_ctrl_regwen_rd_A	40346326	7630	0	0
jitter_enable_rd_A	40346326	16521	0	0
jitter_regwen_rd_A	40346326	7738	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	498746	0	0
T5	11796	866	0	0
T6	713661	0	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T13	0	13463	0	0
T15	0	8040	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	5014	0	0
T35	0	10496	0	0
T50	0	8484	0	0
T78	0	3469	0	0
T79	0	9577	0	0
T80	0	12364	0	0
T81	0	11322	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	9794	0	0
T6	713661	10	0	0
T15	0	192	0	0
T16	0	15	0	0
T27	1853	1	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T48	939	0	0	0
T77	2029	0	0	0
T82	1150	0	0	0
T83	1741	0	0	0
T139	0	15	0	0
T140	0	5	0	0
T141	0	6	0	0
T142	0	503	0	0
T143	0	3	0	0
T144	0	3	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	9128	0	0
T6	713661	1	0	0
T15	0	174	0	0
T16	0	10	0	0
T27	1853	4	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T48	939	0	0	0
T77	2029	0	0	0
T82	1150	0	0	0
T83	1741	0	0	0
T139	0	5	0	0
T140	0	3	0	0
T141	0	7	0	0
T142	0	406	0	0
T144	0	1	0	0
T145	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	11864	0	0
T6	713661	152	0	0
T7	113184	0	0	0
T15	0	239	0	0
T16	0	114	0	0
T31	947	0	0	0
T32	108100	0	0	0
T36	2200	0	0	0
T48	939	0	0	0
T77	2029	0	0	0
T82	1150	0	0	0
T83	1741	0	0	0
T84	1965	0	0	0
T88	0	50	0	0
T97	0	13	0	0
T146	0	71	0	0
T147	0	59	0	0
T148	0	29	0	0
T149	0	34	0	0
T150	0	73	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	7630	0	0
T15	249241	191	0	0
T16	160943	0	0	0
T52	1385	0	0	0
T142	0	319	0	0
T151	0	26	0	0
T152	0	5	0	0
T153	0	35	0	0
T154	0	35	0	0
T155	0	21	0	0
T156	0	8	0	0
T157	0	417	0	0
T158	0	9	0	0
T159	1348	0	0	0
T160	671	0	0	0
T161	1883	0	0	0
T162	2062	0	0	0
T163	1141	0	0	0
T164	3442	0	0	0
T165	1453	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	16521	0	0
T6	713661	126	0	0
T15	0	153	0	0
T16	0	328	0	0
T27	1853	100	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T48	939	0	0	0
T77	2029	0	0	0
T82	1150	0	0	0
T83	1741	0	0	0
T139	0	316	0	0
T140	0	86	0	0
T141	0	55	0	0
T142	0	1144	0	0
T143	0	63	0	0
T144	0	100	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	7738	0	0
T15	249241	111	0	0
T16	160943	0	0	0
T52	1385	0	0	0
T142	0	412	0	0
T154	0	24	0	0
T157	0	468	0	0
T159	1348	0	0	0
T160	671	0	0	0
T161	1883	0	0	0
T162	2062	0	0	0
T163	1141	0	0	0
T164	3442	0	0	0
T165	1453	0	0	0
T166	0	139	0	0
T167	0	237	0	0
T168	0	220	0	0
T169	0	665	0	0
T170	0	472	0	0
T171	0	352	0	0