Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	88028839	3086	0	0
g_div2.Div2Whole_A	88028839	3600	0	0
g_div4.Div4Stepped_A	43200432	3006	0	0
g_div4.Div4Whole_A	43200432	3419	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028839	3086	0	0
T5	19850	4	0	0
T6	564138	36	0	0
T7	0	9	0	0
T8	7511	10	0	0
T9	2115	8	0	0
T26	5177	3	0	0
T27	3705	0	0	0
T28	2105	0	0	0
T29	8459	11	0	0
T30	1914	0	0	0
T31	3639	0	0	0
T77	0	3	0	0
T82	0	1	0	0
T83	0	10	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028839	3600	0	0
T5	19850	5	0	0
T6	564138	47	0	0
T7	0	11	0	0
T8	7511	10	0	0
T9	2115	10	0	0
T26	5177	3	0	0
T27	3705	0	0	0
T28	2105	0	0	0
T29	8459	10	0	0
T30	1914	0	0	0
T31	3639	0	0	0
T77	0	4	0	0
T82	0	1	0	0
T83	0	8	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200432	3006	0	0
T5	8894	4	0	0
T6	282298	36	0	0
T7	0	9	0	0
T8	4032	10	0	0
T9	1148	8	0	0
T26	2718	3	0	0
T27	1813	0	0	0
T28	1034	0	0	0
T29	4688	11	0	0
T30	945	0	0	0
T31	1759	0	0	0
T77	0	3	0	0
T82	0	1	0	0
T83	0	10	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200432	3419	0	0
T5	8894	5	0	0
T6	282298	40	0	0
T7	0	11	0	0
T8	4032	10	0	0
T9	1148	10	0	0
T26	2718	3	0	0
T27	1813	0	0	0
T28	1034	0	0	0
T29	4688	10	0	0
T30	945	0	0	0
T31	1759	0	0	0
T77	0	3	0	0
T82	0	1	0	0
T83	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	88028839	3086	0	0
g_div2.Div2Whole_A	88028839	3600	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028839	3086	0	0
T5	19850	4	0	0
T6	564138	36	0	0
T7	0	9	0	0
T8	7511	10	0	0
T9	2115	8	0	0
T26	5177	3	0	0
T27	3705	0	0	0
T28	2105	0	0	0
T29	8459	11	0	0
T30	1914	0	0	0
T31	3639	0	0	0
T77	0	3	0	0
T82	0	1	0	0
T83	0	10	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028839	3600	0	0
T5	19850	5	0	0
T6	564138	47	0	0
T7	0	11	0	0
T8	7511	10	0	0
T9	2115	10	0	0
T26	5177	3	0	0
T27	3705	0	0	0
T28	2105	0	0	0
T29	8459	10	0	0
T30	1914	0	0	0
T31	3639	0	0	0
T77	0	4	0	0
T82	0	1	0	0
T83	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	43200432	3006	0	0
g_div4.Div4Whole_A	43200432	3419	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200432	3006	0	0
T5	8894	4	0	0
T6	282298	36	0	0
T7	0	9	0	0
T8	4032	10	0	0
T9	1148	8	0	0
T26	2718	3	0	0
T27	1813	0	0	0
T28	1034	0	0	0
T29	4688	11	0	0
T30	945	0	0	0
T31	1759	0	0	0
T77	0	3	0	0
T82	0	1	0	0
T83	0	10	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200432	3419	0	0
T5	8894	5	0	0
T6	282298	40	0	0
T7	0	11	0	0
T8	4032	10	0	0
T9	1148	10	0	0
T26	2718	3	0	0
T27	1813	0	0	0
T28	1034	0	0	0
T29	4688	10	0	0
T30	945	0	0	0
T31	1759	0	0	0
T77	0	3	0	0
T82	0	1	0	0
T83	0	7	0	0