Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	118157088	439	0	0
StatusRise_A	118157088	439	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118157088	439	0	0
T3	188688	0	0	0
T33	7821	0	0	0
T49	2772	0	0	0
T51	4041	3	0	0
T52	0	8	0	0
T53	0	8	0	0
T97	5457	0	0	0
T119	41145	0	0	0
T146	6363	0	0	0
T172	0	13	0	0
T173	0	1	0	0
T174	0	9	0	0
T175	0	11	0	0
T176	0	15	0	0
T177	0	8	0	0
T178	0	2	0	0
T179	0	10	0	0
T180	3318	0	0	0
T181	4380	0	0	0
T182	7080	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118157088	439	0	0
T3	188688	0	0	0
T33	7821	0	0	0
T49	2772	0	0	0
T51	4041	3	0	0
T52	0	8	0	0
T53	0	8	0	0
T97	5457	0	0	0
T119	41145	0	0	0
T146	6363	0	0	0
T172	0	13	0	0
T173	0	1	0	0
T174	0	9	0	0
T175	0	11	0	0
T176	0	15	0	0
T177	0	8	0	0
T178	0	2	0	0
T179	0	10	0	0
T180	3318	0	0	0
T181	4380	0	0	0
T182	7080	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39385696	149	0	0
StatusRise_A	39385696	149	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	149	0	0
T3	62896	0	0	0
T33	2607	0	0	0
T49	924	0	0	0
T51	1347	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T97	1819	0	0	0
T119	13715	0	0	0
T146	2121	0	0	0
T172	0	4	0	0
T174	0	3	0	0
T175	0	3	0	0
T176	0	5	0	0
T177	0	3	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	1106	0	0	0
T181	1460	0	0	0
T182	2360	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	149	0	0
T3	62896	0	0	0
T33	2607	0	0	0
T49	924	0	0	0
T51	1347	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T97	1819	0	0	0
T119	13715	0	0	0
T146	2121	0	0	0
T172	0	4	0	0
T174	0	3	0	0
T175	0	3	0	0
T176	0	5	0	0
T177	0	3	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	1106	0	0	0
T181	1460	0	0	0
T182	2360	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39385696	149	0	0
StatusRise_A	39385696	149	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	149	0	0
T3	62896	0	0	0
T33	2607	0	0	0
T49	924	0	0	0
T51	1347	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T97	1819	0	0	0
T119	13715	0	0	0
T146	2121	0	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0
T177	0	3	0	0
T179	0	4	0	0
T180	1106	0	0	0
T181	1460	0	0	0
T182	2360	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	149	0	0
T3	62896	0	0	0
T33	2607	0	0	0
T49	924	0	0	0
T51	1347	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T97	1819	0	0	0
T119	13715	0	0	0
T146	2121	0	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0
T177	0	3	0	0
T179	0	4	0	0
T180	1106	0	0	0
T181	1460	0	0	0
T182	2360	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39385696	141	0	0
StatusRise_A	39385696	141	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	141	0	0
T3	62896	0	0	0
T33	2607	0	0	0
T49	924	0	0	0
T51	1347	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T97	1819	0	0	0
T119	13715	0	0	0
T146	2121	0	0	0
T172	0	3	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	1106	0	0	0
T181	1460	0	0	0
T182	2360	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39385696	141	0	0
T3	62896	0	0	0
T33	2607	0	0	0
T49	924	0	0	0
T51	1347	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T97	1819	0	0	0
T119	13715	0	0	0
T146	2121	0	0	0
T172	0	3	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	1106	0	0	0
T181	1460	0	0	0
T182	2360	0	0	0