Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	1028666794	33709	0	0
CgEnOn_A	1028666794	24419	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028666794	33709	0	0
T3	256716	0	0	0
T5	173566	66	0	0
T6	4800076	90	0	0
T7	0	13	0	0
T8	62442	3	0	0
T9	17626	3	0	0
T26	42790	3	0	0
T27	30092	7	0	0
T28	17112	7	0	0
T29	70910	3	0	0
T30	15574	6	0	0
T31	29470	8	0	0
T32	102917	0	0	0
T33	86924	0	0	0
T49	6602	0	0	0
T51	2904	5	0	0
T52	0	15	0	0
T53	0	10	0	0
T78	0	5	0	0
T84	0	4	0	0
T97	3790	0	0	0
T119	304786	0	0	0
T146	17680	0	0	0
T172	0	30	0	0
T173	0	5	0	0
T174	0	15	0	0
T175	0	20	0	0
T176	0	25	0	0
T180	9228	0	0	0
T181	3010	0	0	0
T182	4968	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028666794	24419	0	0
T3	441548	0	0	0
T5	165513	49	0	0
T6	4541062	57	0	0
T7	0	13	0	0
T8	58686	0	0	0
T9	16568	0	0	0
T25	0	3	0	0
T26	40202	0	0	0
T27	28241	4	0	0
T28	16059	4	0	0
T29	66681	0	0	0
T30	14617	3	0	0
T31	27651	5	0	0
T32	0	178	0	0
T33	149509	0	0	0
T39	0	24	0	0
T49	11355	0	0	0
T51	4961	8	0	0
T52	0	15	0	0
T53	0	10	0	0
T78	0	5	0	0
T97	6518	0	0	0
T119	478149	0	0	0
T146	30409	0	0	0
T172	0	30	0	0
T173	0	5	0	0
T174	0	15	0	0
T175	0	20	0	0
T176	0	25	0	0
T177	0	3	0	0
T180	15871	7	0	0
T181	5176	0	0	0
T182	8544	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43200033	162	0	0
CgEnOn_A	43200033	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200033	162	0	0
T5	8894	1	0	0
T6	282297	0	0	0
T8	4032	0	0	0
T9	1148	0	0	0
T26	2718	0	0	0
T27	1812	0	0	0
T28	1033	0	0	0
T29	4688	0	0	0
T30	944	0	0	0
T31	1759	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200033	162	0	0
T5	8894	1	0	0
T6	282297	0	0	0
T8	4032	0	0	0
T9	1148	0	0	0
T26	2718	0	0	0
T27	1812	0	0	0
T28	1033	0	0	0
T29	4688	0	0	0
T30	944	0	0	0
T31	1759	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	21599568	162	0	0
CgEnOn_A	21599568	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599568	162	0	0
T5	4446	1	0	0
T6	141141	0	0	0
T8	2015	0	0	0
T9	573	0	0	0
T26	1357	0	0	0
T27	906	0	0	0
T28	517	0	0	0
T29	2342	0	0	0
T30	472	0	0	0
T31	879	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599568	162	0	0
T5	4446	1	0	0
T6	141141	0	0	0
T8	2015	0	0	0
T9	573	0	0	0
T26	1357	0	0	0
T27	906	0	0	0
T28	517	0	0	0
T29	2342	0	0	0
T30	472	0	0	0
T31	879	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	21599568	162	0	0
CgEnOn_A	21599568	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599568	162	0	0
T5	4446	1	0	0
T6	141141	0	0	0
T8	2015	0	0	0
T9	573	0	0	0
T26	1357	0	0	0
T27	906	0	0	0
T28	517	0	0	0
T29	2342	0	0	0
T30	472	0	0	0
T31	879	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599568	162	0	0
T5	4446	1	0	0
T6	141141	0	0	0
T8	2015	0	0	0
T9	573	0	0	0
T26	1357	0	0	0
T27	906	0	0	0
T28	517	0	0	0
T29	2342	0	0	0
T30	472	0	0	0
T31	879	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	21599568	162	0	0
CgEnOn_A	21599568	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599568	162	0	0
T5	4446	1	0	0
T6	141141	0	0	0
T8	2015	0	0	0
T9	573	0	0	0
T26	1357	0	0	0
T27	906	0	0	0
T28	517	0	0	0
T29	2342	0	0	0
T30	472	0	0	0
T31	879	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599568	162	0	0
T5	4446	1	0	0
T6	141141	0	0	0
T8	2015	0	0	0
T9	573	0	0	0
T26	1357	0	0	0
T27	906	0	0	0
T28	517	0	0	0
T29	2342	0	0	0
T30	472	0	0	0
T31	879	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88028435	162	0	0
CgEnOn_A	88028435	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028435	162	0	0
T5	19849	1	0	0
T6	564137	0	0	0
T8	7511	0	0	0
T9	2115	0	0	0
T26	5177	0	0	0
T27	3704	0	0	0
T28	2105	0	0	0
T29	8459	0	0	0
T30	1913	0	0	0
T31	3638	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028435	154	0	0
T3	123219	0	0	0
T33	41723	0	0	0
T49	3168	0	0	0
T51	1373	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T78	0	1	0	0
T97	1819	0	0	0
T119	105974	0	0	0
T146	8486	0	0	0
T172	0	6	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0
T177	0	3	0	0
T180	4429	0	0	0
T181	1444	0	0	0
T182	2384	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97705756	157	0	0
CgEnOn_A	97705756	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	157	0	0
T3	128358	0	0	0
T33	43462	0	0	0
T49	3301	0	0	0
T51	1452	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T78	0	1	0	0
T97	1895	0	0	0
T119	152393	0	0	0
T146	8840	0	0	0
T172	0	4	0	0
T174	0	3	0	0
T175	0	3	0	0
T176	0	5	0	0
T177	0	3	0	0
T178	0	1	0	0
T180	4614	0	0	0
T181	1505	0	0	0
T182	2484	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	149	0	0
T3	128358	0	0	0
T33	43462	0	0	0
T49	3301	0	0	0
T51	1452	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T97	1895	0	0	0
T119	152393	0	0	0
T146	8840	0	0	0
T172	0	4	0	0
T174	0	3	0	0
T175	0	3	0	0
T176	0	5	0	0
T177	0	3	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	4614	0	0	0
T181	1505	0	0	0
T182	2484	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97705756	157	0	0
CgEnOn_A	97705756	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	157	0	0
T3	128358	0	0	0
T33	43462	0	0	0
T49	3301	0	0	0
T51	1452	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T78	0	1	0	0
T97	1895	0	0	0
T119	152393	0	0	0
T146	8840	0	0	0
T172	0	4	0	0
T174	0	3	0	0
T175	0	3	0	0
T176	0	5	0	0
T177	0	3	0	0
T178	0	1	0	0
T180	4614	0	0	0
T181	1505	0	0	0
T182	2484	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	149	0	0
T3	128358	0	0	0
T33	43462	0	0	0
T49	3301	0	0	0
T51	1452	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T97	1895	0	0	0
T119	152393	0	0	0
T146	8840	0	0	0
T172	0	4	0	0
T174	0	3	0	0
T175	0	3	0	0
T176	0	5	0	0
T177	0	3	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	4614	0	0	0
T181	1505	0	0	0
T182	2484	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	46788525	148	0	0
CgEnOn_A	46788525	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46788525	148	0	0
T1	68734	0	0	0
T19	58325	0	0	0
T20	2333	0	0	0
T32	102917	1	0	0
T36	1100	0	0	0
T37	1155	0	0	0
T38	1124	0	0	0
T39	842	0	0	0
T40	1602	0	0	0
T41	1572	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T172	0	3	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0
T177	0	2	0	0
T178	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46788525	144	0	0
T3	61613	0	0	0
T33	20862	0	0	0
T49	1585	0	0	0
T51	684	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T97	909	0	0	0
T119	67389	0	0	0
T146	4243	0	0	0
T172	0	3	0	0
T174	0	3	0	0
T175	0	4	0	0
T176	0	5	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	2214	0	0	0
T181	722	0	0	0
T182	1192	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	21599568	5450	0	0
CgEnOn_A	21599568	3147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599568	5450	0	0
T5	4446	19	0	0
T6	141141	22	0	0
T8	2015	1	0	0
T9	573	1	0	0
T26	1357	1	0	0
T27	906	2	0	0
T28	517	2	0	0
T29	2342	1	0	0
T30	472	1	0	0
T31	879	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21599568	3147	0	0
T5	4446	14	0	0
T6	141141	11	0	0
T8	2015	0	0	0
T9	573	0	0	0
T25	0	1	0	0
T26	1357	0	0	0
T27	906	1	0	0
T28	517	1	0	0
T29	2342	0	0	0
T30	472	0	0	0
T31	879	2	0	0
T32	0	52	0	0
T39	0	8	0	0
T51	0	1	0	0
T180	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43200033	5483	0	0
CgEnOn_A	43200033	3180	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200033	5483	0	0
T5	8894	18	0	0
T6	282297	23	0	0
T8	4032	1	0	0
T9	1148	1	0	0
T26	2718	1	0	0
T27	1812	2	0	0
T28	1033	2	0	0
T29	4688	1	0	0
T30	944	2	0	0
T31	1759	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43200033	3180	0	0
T5	8894	13	0	0
T6	282297	12	0	0
T8	4032	0	0	0
T9	1148	0	0	0
T25	0	1	0	0
T26	2718	0	0	0
T27	1812	1	0	0
T28	1033	1	0	0
T29	4688	0	0	0
T30	944	1	0	0
T31	1759	1	0	0
T32	0	57	0	0
T39	0	7	0	0
T51	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88028435	5463	0	0
CgEnOn_A	88028435	3152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028435	5463	0	0
T5	19849	22	0	0
T6	564137	22	0	0
T8	7511	1	0	0
T9	2115	1	0	0
T26	5177	1	0	0
T27	3704	2	0	0
T28	2105	2	0	0
T29	8459	1	0	0
T30	1913	2	0	0
T31	3638	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88028435	3152	0	0
T5	19849	16	0	0
T6	564137	11	0	0
T8	7511	0	0	0
T9	2115	0	0	0
T25	0	1	0	0
T26	5177	0	0	0
T27	3704	1	0	0
T28	2105	1	0	0
T29	8459	0	0	0
T30	1913	1	0	0
T31	3638	2	0	0
T32	0	49	0	0
T39	0	9	0	0
T51	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T5,T8,T9
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	46788525	5461	0	0
CgEnOn_A	46788525	3148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46788525	5461	0	0
T5	11796	19	0	0
T6	305123	24	0	0
T8	3755	1	0	0
T9	1057	1	0	0
T26	2589	1	0	0
T27	1853	2	0	0
T28	1052	2	0	0
T29	4230	1	0	0
T30	956	2	0	0
T31	1819	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46788525	3148	0	0
T5	11796	13	0	0
T6	305123	13	0	0
T8	3755	0	0	0
T9	1057	0	0	0
T25	0	1	0	0
T26	2589	0	0	0
T27	1853	1	0	0
T28	1052	1	0	0
T29	4230	0	0	0
T30	956	1	0	0
T31	1819	2	0	0
T32	0	56	0	0
T39	0	7	0	0
T51	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T27,T28
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97705756	2695	0	0
CgEnOn_A	97705756	2687	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	2695	0	0
T5	24574	2	0	0
T6	635661	23	0	0
T7	0	13	0	0
T8	7824	0	0	0
T9	2202	0	0	0
T20	0	4	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2192	1	0	0
T29	8812	0	0	0
T30	1993	1	0	0
T31	3790	0	0	0
T32	0	20	0	0
T38	0	5	0	0
T84	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	2687	0	0
T5	24574	2	0	0
T6	635661	23	0	0
T7	0	13	0	0
T8	7824	0	0	0
T9	2202	0	0	0
T20	0	4	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2192	1	0	0
T29	8812	0	0	0
T30	1993	1	0	0
T31	3790	0	0	0
T32	0	20	0	0
T38	0	5	0	0
T84	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T27,T28
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97705756	2607	0	0
CgEnOn_A	97705756	2599	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	2607	0	0
T5	24574	2	0	0
T6	635661	16	0	0
T7	0	12	0	0
T8	7824	0	0	0
T9	2202	0	0	0
T20	0	5	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2192	1	0	0
T29	8812	0	0	0
T30	1993	1	0	0
T31	3790	0	0	0
T32	0	12	0	0
T38	0	4	0	0
T84	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	2599	0	0
T5	24574	2	0	0
T6	635661	16	0	0
T7	0	12	0	0
T8	7824	0	0	0
T9	2202	0	0	0
T20	0	5	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2192	1	0	0
T29	8812	0	0	0
T30	1993	1	0	0
T31	3790	0	0	0
T32	0	12	0	0
T38	0	4	0	0
T84	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T27,T28
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97705756	2661	0	0
CgEnOn_A	97705756	2653	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	2661	0	0
T5	24574	2	0	0
T6	635661	15	0	0
T7	0	11	0	0
T8	7824	0	0	0
T9	2202	0	0	0
T20	0	7	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2192	1	0	0
T29	8812	0	0	0
T30	1993	1	0	0
T31	3790	0	0	0
T32	0	18	0	0
T38	0	4	0	0
T84	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	2653	0	0
T5	24574	2	0	0
T6	635661	15	0	0
T7	0	11	0	0
T8	7824	0	0	0
T9	2202	0	0	0
T20	0	7	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2192	1	0	0
T29	8812	0	0	0
T30	1993	1	0	0
T31	3790	0	0	0
T32	0	18	0	0
T38	0	4	0	0
T84	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T27,T28
1	1	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97705756	2617	0	0
CgEnOn_A	97705756	2609	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	2617	0	0
T5	24574	2	0	0
T6	635661	27	0	0
T7	0	12	0	0
T8	7824	0	0	0
T9	2202	0	0	0
T20	0	5	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2192	1	0	0
T29	8812	0	0	0
T30	1993	1	0	0
T31	3790	0	0	0
T32	0	15	0	0
T38	0	3	0	0
T84	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97705756	2609	0	0
T5	24574	2	0	0
T6	635661	27	0	0
T7	0	12	0	0
T8	7824	0	0	0
T9	2202	0	0	0
T20	0	5	0	0
T26	5393	0	0	0
T27	3859	1	0	0
T28	2192	1	0	0
T29	8812	0	0	0
T30	1993	1	0	0
T31	3790	0	0	0
T32	0	15	0	0
T38	0	3	0	0
T84	0	6	0	0