Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	224095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

528578

1

T6

32

T7

11

T23

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	217740	1			T6	36		T23	19		T24	10
values[0x0]	252933	1			T6	20		T7	9		T23	20
values[0x1]	282000	1			T6	19		T7	18		T23	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155337	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

597336

1

T6

37

T7

12

T23

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3216	1			T6	1		T2	32		T19	5
valid_sources[0x01]	2828	1			T1	5		T2	18		T21	1
valid_sources[0x02]	2339	1			T1	1		T2	26		T3	2
valid_sources[0x03]	3153	1			T1	3		T2	38		T18	5
valid_sources[0x04]	2707	1			T1	6		T2	28		T3	1
valid_sources[0x05]	3137	1			T26	1		T1	1		T2	20
valid_sources[0x06]	3232	1			T2	46		T3	3		T32	1
valid_sources[0x07]	3217	1			T2	20		T3	2		T21	2
valid_sources[0x08]	2795	1			T27	2		T1	3		T2	32
valid_sources[0x09]	2797	1			T6	2		T27	1		T2	27
valid_sources[0x0a]	2652	1			T1	1		T16	1		T2	21
valid_sources[0x0b]	3539	1			T2	24		T18	1		T3	3
valid_sources[0x0c]	6843	1			T1	2		T2	25		T33	13
valid_sources[0x0d]	3097	1			T1	1		T2	25		T3	5
valid_sources[0x0e]	2681	1			T2	25		T17	1		T3	1
valid_sources[0x0f]	2226	1			T1	2		T2	17		T3	1
valid_sources[0x10]	3548	1			T1	2		T2	29		T3	1
valid_sources[0x11]	3169	1			T6	1		T2	15		T3	2
valid_sources[0x12]	2906	1			T1	1		T16	3		T2	17
valid_sources[0x13]	3325	1			T6	2		T1	4		T2	15
valid_sources[0x14]	2579	1			T27	3		T2	28		T19	1
valid_sources[0x15]	2362	1			T6	1		T1	4		T2	22
valid_sources[0x16]	3396	1			T27	7		T2	27		T17	1
valid_sources[0x17]	2811	1			T6	1		T16	2		T2	13
valid_sources[0x18]	3457	1			T2	19		T3	2		T8	1
valid_sources[0x19]	3566	1			T2	21		T18	1		T3	1
valid_sources[0x1a]	5102	1			T1	2		T2	28		T19	1
valid_sources[0x1b]	2573	1			T6	1		T2	22		T17	1
valid_sources[0x1c]	3095	1			T2	17		T3	2		T93	3
valid_sources[0x1d]	3252	1			T1	2		T2	26		T19	1
valid_sources[0x1e]	2859	1			T6	3		T1	2		T2	29
valid_sources[0x1f]	2725	1			T1	1		T2	20		T18	3
valid_sources[0x20]	3093	1			T2	12		T33	1		T8	5
valid_sources[0x21]	2611	1			T1	1		T2	22		T3	3
valid_sources[0x22]	2218	1			T6	1		T26	2		T1	8
valid_sources[0x23]	3270	1			T2	9		T3	1		T8	4
valid_sources[0x24]	3084	1			T1	1		T2	34		T19	2
valid_sources[0x25]	2959	1			T1	1		T2	17		T19	1
valid_sources[0x26]	2281	1			T27	3		T1	2		T2	18
valid_sources[0x27]	3273	1			T6	1		T1	3		T2	18
valid_sources[0x28]	3653	1			T2	15		T3	1		T8	3
valid_sources[0x29]	2433	1			T1	1		T2	16		T3	2
valid_sources[0x2a]	3383	1			T27	1		T1	2		T2	25
valid_sources[0x2b]	2785	1			T1	5		T2	17		T3	2
valid_sources[0x2c]	2658	1			T2	23		T3	1		T8	9
valid_sources[0x2d]	3364	1			T6	2		T2	18		T3	3
valid_sources[0x2e]	2489	1			T1	1		T2	23		T3	1
valid_sources[0x2f]	2427	1			T1	2		T2	16		T3	3
valid_sources[0x30]	2683	1			T1	2		T2	13		T3	1
valid_sources[0x31]	2624	1			T1	12		T2	20		T19	1
valid_sources[0x32]	2980	1			T6	1		T1	1		T2	33
valid_sources[0x33]	2978	1			T2	16		T20	3		T29	2
valid_sources[0x34]	3145	1			T7	27		T2	26		T17	1
valid_sources[0x35]	2679	1			T1	5		T2	15		T3	1
valid_sources[0x36]	3333	1			T1	2		T2	31		T18	4
valid_sources[0x37]	3267	1			T1	7		T2	21		T174	30
valid_sources[0x38]	3110	1			T16	5		T2	22		T19	1
valid_sources[0x39]	2819	1			T6	2		T1	4		T2	27
valid_sources[0x3a]	3046	1			T2	23		T3	1		T29	1
valid_sources[0x3b]	2928	1			T6	1		T2	8		T3	3
valid_sources[0x3c]	2636	1			T6	1		T2	13		T20	1
valid_sources[0x3d]	3125	1			T6	2		T2	16		T3	2
valid_sources[0x3e]	2993	1			T2	24		T3	1		T9	2
valid_sources[0x3f]	2492	1			T1	1		T2	25		T3	2
valid_sources[0x40]	2549	1			T6	1		T2	21		T3	1
valid_sources[0x41]	2467	1			T6	1		T26	1		T1	5
valid_sources[0x42]	2432	1			T1	4		T2	21		T3	1
valid_sources[0x43]	2880	1			T2	37		T19	1		T3	1
valid_sources[0x44]	2912	1			T2	22		T3	1		T33	3
valid_sources[0x45]	2373	1			T1	3		T2	23		T3	2
valid_sources[0x46]	2438	1			T27	2		T1	6		T2	17
valid_sources[0x47]	3070	1			T2	29		T3	1		T8	5
valid_sources[0x48]	3057	1			T27	1		T1	2		T2	24
valid_sources[0x49]	2829	1			T1	2		T2	13		T3	1
valid_sources[0x4a]	2796	1			T2	21		T3	1		T8	3
valid_sources[0x4b]	2549	1			T2	24		T17	2		T19	1
valid_sources[0x4c]	2773	1			T1	4		T16	4		T2	24
valid_sources[0x4d]	2804	1			T1	3		T2	19		T19	3
valid_sources[0x4e]	2681	1			T16	1		T2	25		T3	2
valid_sources[0x4f]	2759	1			T2	42		T17	1		T33	1
valid_sources[0x50]	2728	1			T2	19		T3	3		T8	8
valid_sources[0x51]	2252	1			T1	1		T2	19		T17	1
valid_sources[0x52]	2317	1			T27	1		T1	1		T2	33
valid_sources[0x53]	2325	1			T2	15		T19	3		T3	2
valid_sources[0x54]	2896	1			T2	33		T29	7		T33	1
valid_sources[0x55]	2964	1			T2	16		T29	5		T8	4
valid_sources[0x56]	3518	1			T6	1		T2	32		T3	2
valid_sources[0x57]	3457	1			T6	2		T24	31		T2	17
valid_sources[0x58]	2699	1			T2	26		T19	2		T3	1
valid_sources[0x59]	2625	1			T27	4		T1	4		T2	33
valid_sources[0x5a]	2442	1			T6	1		T2	17		T29	5
valid_sources[0x5b]	3001	1			T25	1		T1	4		T2	19
valid_sources[0x5c]	2390	1			T1	7		T2	30		T3	3
valid_sources[0x5d]	2844	1			T27	1		T1	9		T16	11
valid_sources[0x5e]	3121	1			T6	3		T1	1		T2	39
valid_sources[0x5f]	3378	1			T1	1		T2	29		T21	3
valid_sources[0x60]	2720	1			T2	29		T19	2		T3	4
valid_sources[0x61]	2923	1			T27	4		T1	1		T2	20
valid_sources[0x62]	3078	1			T1	1		T2	30		T19	1
valid_sources[0x63]	2969	1			T2	34		T29	1		T8	7
valid_sources[0x64]	2928	1			T1	2		T2	18		T19	1
valid_sources[0x65]	2833	1			T1	3		T2	31		T32	1
valid_sources[0x66]	3033	1			T2	26		T3	1		T93	5
valid_sources[0x67]	2728	1			T26	1		T1	2		T2	22
valid_sources[0x68]	3474	1			T6	1		T27	1		T1	4
valid_sources[0x69]	2545	1			T25	1		T2	18		T18	1
valid_sources[0x6a]	2674	1			T2	35		T3	2		T8	2
valid_sources[0x6b]	2767	1			T6	1		T1	1		T2	14
valid_sources[0x6c]	2537	1			T1	6		T2	41		T3	2
valid_sources[0x6d]	2727	1			T26	1		T2	15		T8	4
valid_sources[0x6e]	2958	1			T1	1		T2	29		T18	1
valid_sources[0x6f]	2689	1			T1	4		T16	2		T2	34
valid_sources[0x70]	3208	1			T2	35		T21	1		T29	1
valid_sources[0x71]	2688	1			T6	2		T1	3		T16	5
valid_sources[0x72]	2344	1			T1	2		T2	20		T29	2
valid_sources[0x73]	2960	1			T2	30		T3	1		T105	2
valid_sources[0x74]	2502	1			T6	1		T2	19		T3	2
valid_sources[0x75]	3107	1			T2	26		T3	1		T8	3
valid_sources[0x76]	5391	1			T2	29		T18	2		T3	3
valid_sources[0x77]	3446	1			T6	1		T1	1		T2	9
valid_sources[0x78]	4310	1			T1	1		T2	25		T33	1
valid_sources[0x79]	2640	1			T1	9		T2	24		T19	1
valid_sources[0x7a]	2491	1			T25	1		T26	1		T27	1
valid_sources[0x7b]	2922	1			T27	2		T1	2		T2	25
valid_sources[0x7c]	2537	1			T26	1		T2	32		T19	1
valid_sources[0x7d]	2377	1			T1	1		T2	17		T18	1
valid_sources[0x7e]	4009	1			T2	28		T3	1		T8	1
valid_sources[0x7f]	2920	1			T1	1		T2	16		T19	1
valid_sources[0x80]	2710	1			T26	2		T1	4		T2	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

147168

1

T6

21

T23

11

T24

2

values[0x0]

all_enables

biggest_size

203733

1

T6

7

T7

4

T23

5

values[0x1]

all_enables

biggest_size

177677

1

T6

4

T7

7

T23

2