Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T4
0	1	Covered	T26,T2,T17
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T2
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	190172634	8884	0	0
GateOpen_A	190172634	15834	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190172634	8884	0	0
T2	0	39	0	0
T4	28769	0	0	0
T5	2892	16	0	0
T6	7314	0	0	0
T7	3539	0	0	0
T10	0	66	0	0
T17	0	45	0	0
T18	0	27	0	0
T19	0	4	0	0
T23	6575	0	0	0
T24	7074	0	0	0
T25	39368	0	0	0
T26	7438	20	0	0
T27	4804	0	0	0
T28	4266	0	0	0
T32	0	15	0	0
T43	0	26	0	0
T162	0	22	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190172634	15834	0	0
T2	0	55	0	0
T4	28769	12	0	0
T5	2892	20	0	0
T6	7314	4	0	0
T7	3539	0	0	0
T16	0	4	0	0
T17	0	45	0	0
T18	0	31	0	0
T23	6575	0	0	0
T24	7074	0	0	0
T25	39368	4	0	0
T26	7438	20	0	0
T27	4804	0	0	0
T28	4266	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T4
0	1	Covered	T26,T2,T17
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T2
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	20513654	2115	0	0
GateOpen_A	20513654	3849	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513654	2115	0	0
T2	0	9	0	0
T4	2551	0	0	0
T5	315	4	0	0
T6	899	0	0	0
T7	378	0	0	0
T10	0	11	0	0
T17	0	10	0	0
T18	0	7	0	0
T19	0	1	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	0	0	0
T26	811	5	0	0
T27	521	0	0	0
T28	459	0	0	0
T32	0	4	0	0
T43	0	7	0	0
T162	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513654	3849	0	0
T2	0	13	0	0
T4	2551	3	0	0
T5	315	5	0	0
T6	899	1	0	0
T7	378	0	0	0
T16	0	1	0	0
T17	0	10	0	0
T18	0	8	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	1	0	0
T26	811	5	0	0
T27	521	0	0	0
T28	459	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T4
0	1	Covered	T26,T2,T17
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T2
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	41027745	2274	0	0
GateOpen_A	41027745	4008	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027745	2274	0	0
T2	0	10	0	0
T4	5101	0	0	0
T5	629	4	0	0
T6	1802	0	0	0
T7	755	0	0	0
T10	0	18	0	0
T17	0	13	0	0
T18	0	7	0	0
T19	0	1	0	0
T23	1540	0	0	0
T24	1578	0	0	0
T25	8708	0	0	0
T26	1622	5	0	0
T27	1041	0	0	0
T28	917	0	0	0
T32	0	4	0	0
T43	0	7	0	0
T162	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027745	4008	0	0
T2	0	14	0	0
T4	5101	3	0	0
T5	629	5	0	0
T6	1802	1	0	0
T7	755	0	0	0
T16	0	1	0	0
T17	0	13	0	0
T18	0	8	0	0
T23	1540	0	0	0
T24	1578	0	0	0
T25	8708	1	0	0
T26	1622	5	0	0
T27	1041	0	0	0
T28	917	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T4
0	1	Covered	T26,T2,T17
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T2
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	83935758	2250	0	0
GateOpen_A	83935758	3991	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935758	2250	0	0
T2	0	11	0	0
T4	14078	0	0	0
T5	1297	4	0	0
T6	3075	0	0	0
T7	1604	0	0	0
T10	0	17	0	0
T17	0	11	0	0
T18	0	7	0	0
T19	0	1	0	0
T23	2844	0	0	0
T24	3138	0	0	0
T25	17537	0	0	0
T26	3337	5	0	0
T27	2161	0	0	0
T28	1927	0	0	0
T32	0	3	0	0
T43	0	7	0	0
T162	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935758	3991	0	0
T2	0	15	0	0
T4	14078	3	0	0
T5	1297	5	0	0
T6	3075	1	0	0
T7	1604	0	0	0
T16	0	1	0	0
T17	0	11	0	0
T18	0	8	0	0
T23	2844	0	0	0
T24	3138	0	0	0
T25	17537	1	0	0
T26	3337	5	0	0
T27	2161	0	0	0
T28	1927	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T26,T4
0	1	Covered	T26,T2,T17
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T2
1	0	Covered	T5,T43,T44
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	44695477	2245	0	0
GateOpen_A	44695477	3986	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44695477	2245	0	0
T2	0	9	0	0
T4	7039	0	0	0
T5	651	4	0	0
T6	1538	0	0	0
T7	802	0	0	0
T10	0	20	0	0
T17	0	11	0	0
T18	0	6	0	0
T19	0	1	0	0
T23	1423	0	0	0
T24	1569	0	0	0
T25	8769	0	0	0
T26	1668	5	0	0
T27	1081	0	0	0
T28	963	0	0	0
T32	0	4	0	0
T43	0	5	0	0
T162	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44695477	3986	0	0
T2	0	13	0	0
T4	7039	3	0	0
T5	651	5	0	0
T6	1538	1	0	0
T7	802	0	0	0
T16	0	1	0	0
T17	0	11	0	0
T18	0	7	0	0
T23	1423	0	0	0
T24	1569	0	0	0
T25	8769	1	0	0
T26	1668	5	0	0
T27	1081	0	0	0
T28	963	1	0	0