Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	199059750	31748	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199059750	31748	0	0
T1	281270	134	0	0
T2	968325	220	0	0
T3	222855	187	0	0
T9	0	58	0	0
T10	0	281	0	0
T11	0	195	0	0
T12	0	41	0	0
T13	0	50	0	0
T14	0	46	0	0
T15	0	89	0	0
T16	13085	0	0	0
T17	6545	0	0	0
T18	9025	0	0	0
T19	9750	0	0	0
T20	12170	0	0	0
T21	51405	0	0	0
T22	16005	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39811950	4709	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	4709	0	0
T1	56254	21	0	0
T2	193665	31	0	0
T3	44571	30	0	0
T9	0	8	0	0
T10	0	36	0	0
T11	0	27	0	0
T12	0	8	0	0
T13	0	8	0	0
T14	0	8	0	0
T15	0	13	0	0
T16	2617	0	0	0
T17	1309	0	0	0
T18	1805	0	0	0
T19	1950	0	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39811950	4597	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	4597	0	0
T1	56254	21	0	0
T2	193665	31	0	0
T3	44571	29	0	0
T9	0	8	0	0
T10	0	36	0	0
T11	0	26	0	0
T12	0	8	0	0
T13	0	8	0	0
T14	0	8	0	0
T15	0	11	0	0
T16	2617	0	0	0
T17	1309	0	0	0
T18	1805	0	0	0
T19	1950	0	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39811950	6416	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	6416	0	0
T1	56254	27	0	0
T2	193665	45	0	0
T3	44571	37	0	0
T9	0	11	0	0
T10	0	56	0	0
T11	0	44	0	0
T12	0	8	0	0
T13	0	10	0	0
T14	0	9	0	0
T15	0	18	0	0
T16	2617	0	0	0
T17	1309	0	0	0
T18	1805	0	0	0
T19	1950	0	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39811950	6369	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	6369	0	0
T1	56254	27	0	0
T2	193665	44	0	0
T3	44571	37	0	0
T9	0	12	0	0
T10	0	55	0	0
T11	0	38	0	0
T12	0	8	0	0
T13	0	10	0	0
T14	0	10	0	0
T15	0	18	0	0
T16	2617	0	0	0
T17	1309	0	0	0
T18	1805	0	0	0
T19	1950	0	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39811950	9657	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	9657	0	0
T1	56254	38	0	0
T2	193665	69	0	0
T3	44571	54	0	0
T9	0	19	0	0
T10	0	98	0	0
T11	0	60	0	0
T12	0	9	0	0
T13	0	14	0	0
T14	0	11	0	0
T15	0	29	0	0
T16	2617	0	0	0
T17	1309	0	0	0
T18	1805	0	0	0
T19	1950	0	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0