Line Coverage for Module :
clkmgr_sec_cm_checker_assert
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 23 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
23 |
1 |
1 |
Cond Coverage for Module :
clkmgr_sec_cm_checker_assert
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 23
EXPRESSION (((!rst_ni)) || disable_sva)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T2,T8 |
Assert Coverage for Module :
clkmgr_sec_cm_checker_assert
Assertion Details
AllClkBypReqFalse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39811950 |
37177071 |
0 |
0 |
T4 |
9385 |
1907 |
0 |
0 |
T5 |
1511 |
1384 |
0 |
0 |
T6 |
2754 |
2310 |
0 |
0 |
T7 |
1603 |
1467 |
0 |
0 |
T23 |
2934 |
2505 |
0 |
0 |
T24 |
1634 |
1510 |
0 |
0 |
T25 |
912 |
904 |
0 |
0 |
T26 |
868 |
825 |
0 |
0 |
T27 |
2229 |
2089 |
0 |
0 |
T28 |
1303 |
1165 |
0 |
0 |
AllClkBypReqTrue_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39811950 |
85427 |
0 |
0 |
T1 |
56254 |
0 |
0 |
0 |
T2 |
0 |
1061 |
0 |
0 |
T4 |
9385 |
0 |
0 |
0 |
T6 |
2754 |
372 |
0 |
0 |
T7 |
1603 |
0 |
0 |
0 |
T10 |
0 |
446 |
0 |
0 |
T20 |
0 |
497 |
0 |
0 |
T23 |
2934 |
317 |
0 |
0 |
T24 |
1634 |
60 |
0 |
0 |
T25 |
912 |
0 |
0 |
0 |
T26 |
868 |
0 |
0 |
0 |
T27 |
2229 |
0 |
0 |
0 |
T28 |
1303 |
0 |
0 |
0 |
T93 |
0 |
263 |
0 |
0 |
T103 |
0 |
386 |
0 |
0 |
T104 |
0 |
95 |
0 |
0 |
T105 |
0 |
24 |
0 |
0 |
IoClkBypReqFalse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39811950 |
37115978 |
0 |
2415 |
T4 |
9385 |
1901 |
0 |
3 |
T5 |
1511 |
1382 |
0 |
3 |
T6 |
2754 |
2049 |
0 |
3 |
T7 |
1603 |
1465 |
0 |
3 |
T23 |
2934 |
2233 |
0 |
3 |
T24 |
1634 |
1507 |
0 |
3 |
T25 |
912 |
902 |
0 |
3 |
T26 |
868 |
823 |
0 |
3 |
T27 |
2229 |
2087 |
0 |
3 |
T28 |
1303 |
1163 |
0 |
3 |
IoClkBypReqTrue_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39811950 |
141638 |
0 |
0 |
T1 |
56254 |
0 |
0 |
0 |
T2 |
0 |
1044 |
0 |
0 |
T4 |
9385 |
0 |
0 |
0 |
T6 |
2754 |
631 |
0 |
0 |
T7 |
1603 |
0 |
0 |
0 |
T10 |
0 |
878 |
0 |
0 |
T20 |
0 |
594 |
0 |
0 |
T23 |
2934 |
587 |
0 |
0 |
T24 |
1634 |
61 |
0 |
0 |
T25 |
912 |
0 |
0 |
0 |
T26 |
868 |
0 |
0 |
0 |
T27 |
2229 |
0 |
0 |
0 |
T28 |
1303 |
0 |
0 |
0 |
T93 |
0 |
84 |
0 |
0 |
T103 |
0 |
434 |
0 |
0 |
T104 |
0 |
30 |
0 |
0 |
T105 |
0 |
232 |
0 |
0 |
LcClkBypAckFalse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39811950 |
37182805 |
0 |
0 |
T4 |
9385 |
1907 |
0 |
0 |
T5 |
1511 |
1384 |
0 |
0 |
T6 |
2754 |
2273 |
0 |
0 |
T7 |
1603 |
1467 |
0 |
0 |
T23 |
2934 |
2548 |
0 |
0 |
T24 |
1634 |
1570 |
0 |
0 |
T25 |
912 |
904 |
0 |
0 |
T26 |
868 |
825 |
0 |
0 |
T27 |
2229 |
2089 |
0 |
0 |
T28 |
1303 |
1165 |
0 |
0 |
LcClkBypAckTrue_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39811950 |
79693 |
0 |
0 |
T1 |
56254 |
0 |
0 |
0 |
T2 |
0 |
651 |
0 |
0 |
T4 |
9385 |
0 |
0 |
0 |
T6 |
2754 |
409 |
0 |
0 |
T7 |
1603 |
0 |
0 |
0 |
T10 |
0 |
537 |
0 |
0 |
T20 |
0 |
287 |
0 |
0 |
T23 |
2934 |
274 |
0 |
0 |
T24 |
1634 |
0 |
0 |
0 |
T25 |
912 |
0 |
0 |
0 |
T26 |
868 |
0 |
0 |
0 |
T27 |
2229 |
0 |
0 |
0 |
T28 |
1303 |
0 |
0 |
0 |
T93 |
0 |
76 |
0 |
0 |
T103 |
0 |
294 |
0 |
0 |
T104 |
0 |
26 |
0 |
0 |
T105 |
0 |
113 |
0 |
0 |
T106 |
0 |
92 |
0 |
0 |