Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	372289848	11145	0	0
TransStop_A	372289848	5849	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372289848	11145	0	0
T1	937596	0	0	0
T2	1436928	24	0	0
T3	713152	0	0	0
T4	58660	0	0	0
T10	0	8	0	0
T16	10904	34	0	0
T17	10912	0	0	0
T18	7524	0	0	0
T19	31220	4	0	0
T22	0	32	0	0
T27	9008	12	0	0
T28	8028	0	0	0
T52	0	14	0	0
T53	0	10	0	0
T54	0	12	0	0
T107	0	3	0	0
T108	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372289848	5849	0	0
T1	937596	0	0	0
T2	1436928	8	0	0
T3	713152	0	0	0
T4	58660	0	0	0
T10	0	4	0	0
T16	10904	12	0	0
T17	10912	0	0	0
T18	7524	0	0	0
T19	31220	4	0	0
T22	0	17	0	0
T27	9008	8	0	0
T28	8028	0	0	0
T52	0	10	0	0
T53	0	5	0	0
T54	0	4	0	0
T107	0	1	0	0
T108	0	4	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	93072462	2815	0	0
TransStop_A	93072462	1495	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072462	2815	0	0
T1	234399	0	0	0
T2	359232	5	0	0
T3	178288	0	0	0
T4	14665	0	0	0
T10	0	2	0	0
T16	2726	7	0	0
T17	2728	0	0	0
T18	1881	0	0	0
T19	7805	1	0	0
T22	0	8	0	0
T27	2252	3	0	0
T28	2007	0	0	0
T52	0	4	0	0
T53	0	3	0	0
T107	0	2	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072462	1495	0	0
T1	234399	0	0	0
T2	359232	1	0	0
T3	178288	0	0	0
T4	14665	0	0	0
T10	0	1	0	0
T16	2726	3	0	0
T17	2728	0	0	0
T18	1881	0	0	0
T19	7805	1	0	0
T22	0	6	0	0
T27	2252	2	0	0
T28	2007	0	0	0
T52	0	2	0	0
T53	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	93072462	2790	0	0
TransStop_A	93072462	1455	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072462	2790	0	0
T1	234399	0	0	0
T2	359232	5	0	0
T3	178288	0	0	0
T4	14665	0	0	0
T10	0	2	0	0
T16	2726	11	0	0
T17	2728	0	0	0
T18	1881	0	0	0
T19	7805	1	0	0
T22	0	8	0	0
T27	2252	2	0	0
T28	2007	0	0	0
T52	0	4	0	0
T53	0	1	0	0
T54	0	6	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072462	1455	0	0
T1	234399	0	0	0
T2	359232	1	0	0
T3	178288	0	0	0
T4	14665	0	0	0
T10	0	1	0	0
T16	2726	4	0	0
T17	2728	0	0	0
T18	1881	0	0	0
T19	7805	1	0	0
T22	0	5	0	0
T27	2252	1	0	0
T28	2007	0	0	0
T52	0	2	0	0
T54	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	93072462	2734	0	0
TransStop_A	93072462	1426	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072462	2734	0	0
T1	234399	0	0	0
T2	359232	7	0	0
T3	178288	0	0	0
T4	14665	0	0	0
T10	0	2	0	0
T16	2726	8	0	0
T17	2728	0	0	0
T18	1881	0	0	0
T19	7805	1	0	0
T22	0	8	0	0
T27	2252	3	0	0
T28	2007	0	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	6	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072462	1426	0	0
T1	234399	0	0	0
T2	359232	3	0	0
T3	178288	0	0	0
T4	14665	0	0	0
T10	0	1	0	0
T16	2726	3	0	0
T17	2728	0	0	0
T18	1881	0	0	0
T19	7805	1	0	0
T22	0	3	0	0
T27	2252	2	0	0
T28	2007	0	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0
T108	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	93072462	2806	0	0
TransStop_A	93072462	1473	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072462	2806	0	0
T1	234399	0	0	0
T2	359232	7	0	0
T3	178288	0	0	0
T4	14665	0	0	0
T10	0	2	0	0
T16	2726	8	0	0
T17	2728	0	0	0
T18	1881	0	0	0
T19	7805	1	0	0
T22	0	8	0	0
T27	2252	4	0	0
T28	2007	0	0	0
T52	0	3	0	0
T53	0	3	0	0
T107	0	1	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072462	1473	0	0
T1	234399	0	0	0
T2	359232	3	0	0
T3	178288	0	0	0
T4	14665	0	0	0
T10	0	1	0	0
T16	2726	2	0	0
T17	2728	0	0	0
T18	1881	0	0	0
T19	7805	1	0	0
T22	0	3	0	0
T27	2252	3	0	0
T28	2007	0	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	1	0	0
T108	0	1	0	0