Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T23,T24 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T23,T24 |
1 | 1 | Covered | T6,T23,T24 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T23,T24 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
102344601 |
102342186 |
0 |
0 |
selKnown1 |
251805876 |
251803461 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
102344601 |
102342186 |
0 |
0 |
T4 |
12752 |
12749 |
0 |
0 |
T5 |
1572 |
1569 |
0 |
0 |
T6 |
4226 |
4223 |
0 |
0 |
T7 |
1887 |
1884 |
0 |
0 |
T23 |
3696 |
3693 |
0 |
0 |
T24 |
3888 |
3885 |
0 |
0 |
T25 |
21770 |
21767 |
0 |
0 |
T26 |
4055 |
4052 |
0 |
0 |
T27 |
2602 |
2599 |
0 |
0 |
T28 |
2290 |
2287 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
251805876 |
251803461 |
0 |
0 |
T4 |
42234 |
42231 |
0 |
0 |
T5 |
3888 |
3885 |
0 |
0 |
T6 |
9222 |
9219 |
0 |
0 |
T7 |
4809 |
4806 |
0 |
0 |
T23 |
8532 |
8529 |
0 |
0 |
T24 |
9414 |
9411 |
0 |
0 |
T25 |
52608 |
52605 |
0 |
0 |
T26 |
10011 |
10008 |
0 |
0 |
T27 |
6483 |
6480 |
0 |
0 |
T28 |
5778 |
5775 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
41027343 |
41026538 |
0 |
0 |
selKnown1 |
83935292 |
83934487 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
41027343 |
41026538 |
0 |
0 |
T4 |
5101 |
5100 |
0 |
0 |
T5 |
629 |
628 |
0 |
0 |
T6 |
1802 |
1801 |
0 |
0 |
T7 |
755 |
754 |
0 |
0 |
T23 |
1539 |
1538 |
0 |
0 |
T24 |
1577 |
1576 |
0 |
0 |
T25 |
8708 |
8707 |
0 |
0 |
T26 |
1622 |
1621 |
0 |
0 |
T27 |
1041 |
1040 |
0 |
0 |
T28 |
916 |
915 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
83935292 |
83934487 |
0 |
0 |
T4 |
14078 |
14077 |
0 |
0 |
T5 |
1296 |
1295 |
0 |
0 |
T6 |
3074 |
3073 |
0 |
0 |
T7 |
1603 |
1602 |
0 |
0 |
T23 |
2844 |
2843 |
0 |
0 |
T24 |
3138 |
3137 |
0 |
0 |
T25 |
17536 |
17535 |
0 |
0 |
T26 |
3337 |
3336 |
0 |
0 |
T27 |
2161 |
2160 |
0 |
0 |
T28 |
1926 |
1925 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T23,T24 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T6,T23,T24 |
1 | 1 | Covered | T6,T23,T24 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T23,T24 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
40803989 |
40803184 |
0 |
0 |
selKnown1 |
83935292 |
83934487 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
40803989 |
40803184 |
0 |
0 |
T4 |
5101 |
5100 |
0 |
0 |
T5 |
629 |
628 |
0 |
0 |
T6 |
1525 |
1524 |
0 |
0 |
T7 |
755 |
754 |
0 |
0 |
T23 |
1389 |
1388 |
0 |
0 |
T24 |
1522 |
1521 |
0 |
0 |
T25 |
8708 |
8707 |
0 |
0 |
T26 |
1622 |
1621 |
0 |
0 |
T27 |
1041 |
1040 |
0 |
0 |
T28 |
916 |
915 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
83935292 |
83934487 |
0 |
0 |
T4 |
14078 |
14077 |
0 |
0 |
T5 |
1296 |
1295 |
0 |
0 |
T6 |
3074 |
3073 |
0 |
0 |
T7 |
1603 |
1602 |
0 |
0 |
T23 |
2844 |
2843 |
0 |
0 |
T24 |
3138 |
3137 |
0 |
0 |
T25 |
17536 |
17535 |
0 |
0 |
T26 |
3337 |
3336 |
0 |
0 |
T27 |
2161 |
2160 |
0 |
0 |
T28 |
1926 |
1925 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
20513269 |
20512464 |
0 |
0 |
selKnown1 |
83935292 |
83934487 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20513269 |
20512464 |
0 |
0 |
T4 |
2550 |
2549 |
0 |
0 |
T5 |
314 |
313 |
0 |
0 |
T6 |
899 |
898 |
0 |
0 |
T7 |
377 |
376 |
0 |
0 |
T23 |
768 |
767 |
0 |
0 |
T24 |
789 |
788 |
0 |
0 |
T25 |
4354 |
4353 |
0 |
0 |
T26 |
811 |
810 |
0 |
0 |
T27 |
520 |
519 |
0 |
0 |
T28 |
458 |
457 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
83935292 |
83934487 |
0 |
0 |
T4 |
14078 |
14077 |
0 |
0 |
T5 |
1296 |
1295 |
0 |
0 |
T6 |
3074 |
3073 |
0 |
0 |
T7 |
1603 |
1602 |
0 |
0 |
T23 |
2844 |
2843 |
0 |
0 |
T24 |
3138 |
3137 |
0 |
0 |
T25 |
17536 |
17535 |
0 |
0 |
T26 |
3337 |
3336 |
0 |
0 |
T27 |
2161 |
2160 |
0 |
0 |
T28 |
1926 |
1925 |
0 |
0 |