Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	40731842	564291	0	0
clk_enables_rd_A	40731842	8137	0	0
clk_hints_rd_A	40731842	6829	0	0
extclk_ctrl_rd_A	40731842	12012	0	0
extclk_ctrl_regwen_rd_A	40731842	6151	0	0
jitter_enable_rd_A	40731842	17501	0	0
jitter_regwen_rd_A	40731842	6931	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40731842	564291	0	0
T2	193665	5975	0	0
T3	44571	0	0	0
T9	22455	0	0	0
T10	0	13866	0	0
T13	0	4754	0	0
T17	1309	0	0	0
T18	1805	0	0	0
T19	1950	0	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0
T32	947	0	0	0
T34	0	1886	0	0
T67	0	7979	0	0
T68	0	9420	0	0
T69	0	11671	0	0
T70	0	4485	0	0
T71	0	5744	0	0
T72	0	1328	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40731842	8137	0	0
T3	44571	0	0	0
T9	22455	0	0	0
T19	1950	1	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0
T29	38669	0	0	0
T32	947	0	0	0
T68	0	403	0	0
T70	0	108	0	0
T93	2152	0	0	0
T107	977	0	0	0
T108	0	2	0	0
T128	0	3	0	0
T129	0	5	0	0
T130	0	2	0	0
T131	0	2	0	0
T132	0	241	0	0
T133	0	184	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40731842	6829	0	0
T3	44571	0	0	0
T9	22455	0	0	0
T19	1950	1	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0
T29	38669	0	0	0
T32	947	0	0	0
T68	0	376	0	0
T70	0	111	0	0
T93	2152	0	0	0
T107	977	0	0	0
T108	0	8	0	0
T128	0	2	0	0
T129	0	4	0	0
T130	0	4	0	0
T132	0	192	0	0
T133	0	130	0	0
T134	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40731842	12012	0	0
T1	56254	0	0	0
T2	193665	0	0	0
T4	9385	13	0	0
T16	2617	0	0	0
T20	0	56	0	0
T23	2934	13	0	0
T24	1634	26	0	0
T25	912	0	0	0
T26	868	0	0	0
T27	2229	0	0	0
T28	1303	0	0	0
T55	0	45	0	0
T74	0	37	0	0
T93	0	38	0	0
T103	0	45	0	0
T110	0	19	0	0
T135	0	9	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40731842	6151	0	0
T1	56254	0	0	0
T2	193665	0	0	0
T3	44571	0	0	0
T4	9385	3	0	0
T16	2617	0	0	0
T17	1309	0	0	0
T18	1805	0	0	0
T19	1950	0	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T68	0	275	0	0
T70	0	99	0	0
T74	0	6	0	0
T132	0	187	0	0
T133	0	156	0	0
T136	0	14	0	0
T137	0	33	0	0
T138	0	295	0	0
T139	0	433	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40731842	17501	0	0
T3	44571	0	0	0
T9	22455	0	0	0
T19	1950	82	0	0
T20	2434	0	0	0
T21	10281	0	0	0
T22	3201	0	0	0
T29	38669	0	0	0
T32	947	0	0	0
T68	0	644	0	0
T70	0	317	0	0
T93	2152	0	0	0
T107	977	0	0	0
T108	0	122	0	0
T128	0	101	0	0
T129	0	100	0	0
T130	0	144	0	0
T131	0	52	0	0
T140	0	85	0	0
T141	0	69	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40731842	6931	0	0
T49	16173	0	0	0
T68	355915	363	0	0
T70	0	111	0	0
T132	0	287	0	0
T133	0	225	0	0
T138	0	374	0	0
T139	0	500	0	0
T142	0	65	0	0
T143	0	244	0	0
T144	0	378	0	0
T145	0	232	0	0
T146	1039	0	0	0
T147	68362	0	0	0
T148	51094	0	0	0
T149	77995	0	0	0
T150	2284	0	0	0
T151	1699	0	0	0
T152	1150	0	0	0
T153	2150	0	0	0