Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T23
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	83935758	3026	0	0
g_div2.Div2Whole_A	83935758	3528	0	0
g_div4.Div4Stepped_A	41027745	2962	0	0
g_div4.Div4Whole_A	41027745	3376	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935758	3026	0	0
T1	225016	0	0	0
T2	0	24	0	0
T4	14078	0	0	0
T6	3075	13	0	0
T7	1604	0	0	0
T10	0	19	0	0
T20	0	9	0	0
T23	2844	8	0	0
T24	3138	3	0	0
T25	17537	0	0	0
T26	3337	0	0	0
T27	2161	0	0	0
T28	1927	0	0	0
T93	0	9	0	0
T103	0	14	0	0
T104	0	3	0	0
T105	0	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935758	3528	0	0
T1	225016	0	0	0
T2	0	25	0	0
T4	14078	0	0	0
T6	3075	15	0	0
T7	1604	0	0	0
T10	0	24	0	0
T20	0	11	0	0
T23	2844	13	0	0
T24	3138	3	0	0
T25	17537	0	0	0
T26	3337	0	0	0
T27	2161	0	0	0
T28	1927	0	0	0
T93	0	9	0	0
T103	0	14	0	0
T104	0	11	0	0
T105	0	4	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027745	2962	0	0
T1	112475	0	0	0
T2	0	24	0	0
T4	5101	0	0	0
T6	1802	13	0	0
T7	755	0	0	0
T10	0	19	0	0
T20	0	9	0	0
T23	1540	8	0	0
T24	1578	3	0	0
T25	8708	0	0	0
T26	1622	0	0	0
T27	1041	0	0	0
T28	917	0	0	0
T93	0	9	0	0
T103	0	14	0	0
T104	0	3	0	0
T105	0	4	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027745	3376	0	0
T1	112475	0	0	0
T2	0	25	0	0
T4	5101	0	0	0
T6	1802	15	0	0
T7	755	0	0	0
T10	0	19	0	0
T20	0	11	0	0
T23	1540	12	0	0
T24	1578	3	0	0
T25	8708	0	0	0
T26	1622	0	0	0
T27	1041	0	0	0
T28	917	0	0	0
T93	0	9	0	0
T103	0	14	0	0
T104	0	9	0	0
T105	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T23
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	83935758	3026	0	0
g_div2.Div2Whole_A	83935758	3528	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935758	3026	0	0
T1	225016	0	0	0
T2	0	24	0	0
T4	14078	0	0	0
T6	3075	13	0	0
T7	1604	0	0	0
T10	0	19	0	0
T20	0	9	0	0
T23	2844	8	0	0
T24	3138	3	0	0
T25	17537	0	0	0
T26	3337	0	0	0
T27	2161	0	0	0
T28	1927	0	0	0
T93	0	9	0	0
T103	0	14	0	0
T104	0	3	0	0
T105	0	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935758	3528	0	0
T1	225016	0	0	0
T2	0	25	0	0
T4	14078	0	0	0
T6	3075	15	0	0
T7	1604	0	0	0
T10	0	24	0	0
T20	0	11	0	0
T23	2844	13	0	0
T24	3138	3	0	0
T25	17537	0	0	0
T26	3337	0	0	0
T27	2161	0	0	0
T28	1927	0	0	0
T93	0	9	0	0
T103	0	14	0	0
T104	0	11	0	0
T105	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T23
1	0	Covered	T6,T23,T24
1	1	Covered	T6,T23,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	41027745	2962	0	0
g_div4.Div4Whole_A	41027745	3376	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027745	2962	0	0
T1	112475	0	0	0
T2	0	24	0	0
T4	5101	0	0	0
T6	1802	13	0	0
T7	755	0	0	0
T10	0	19	0	0
T20	0	9	0	0
T23	1540	8	0	0
T24	1578	3	0	0
T25	8708	0	0	0
T26	1622	0	0	0
T27	1041	0	0	0
T28	917	0	0	0
T93	0	9	0	0
T103	0	14	0	0
T104	0	3	0	0
T105	0	4	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027745	3376	0	0
T1	112475	0	0	0
T2	0	25	0	0
T4	5101	0	0	0
T6	1802	15	0	0
T7	755	0	0	0
T10	0	19	0	0
T20	0	11	0	0
T23	1540	12	0	0
T24	1578	3	0	0
T25	8708	0	0	0
T26	1622	0	0	0
T27	1041	0	0	0
T28	917	0	0	0
T93	0	9	0	0
T103	0	14	0	0
T104	0	9	0	0
T105	0	4	0	0