Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	119435850	417	0	0
StatusRise_A	119435850	417	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119435850	417	0	0
T4	28155	0	0	0
T5	4533	13	0	0
T6	8262	0	0	0
T7	4809	0	0	0
T23	8802	0	0	0
T24	4902	0	0	0
T25	2736	0	0	0
T26	2604	0	0	0
T27	6687	0	0	0
T28	3909	0	0	0
T43	0	14	0	0
T44	0	2	0	0
T45	0	2	0	0
T154	0	15	0	0
T155	0	12	0	0
T156	0	8	0	0
T157	0	5	0	0
T158	0	2	0	0
T159	0	6	0	0
T160	0	6	0	0
T161	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119435850	417	0	0
T4	28155	0	0	0
T5	4533	13	0	0
T6	8262	0	0	0
T7	4809	0	0	0
T23	8802	0	0	0
T24	4902	0	0	0
T25	2736	0	0	0
T26	2604	0	0	0
T27	6687	0	0	0
T28	3909	0	0	0
T43	0	14	0	0
T44	0	2	0	0
T45	0	2	0	0
T154	0	15	0	0
T155	0	12	0	0
T156	0	8	0	0
T157	0	5	0	0
T158	0	2	0	0
T159	0	6	0	0
T160	0	6	0	0
T161	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39811950	140	0	0
StatusRise_A	39811950	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	140	0	0
T4	9385	0	0	0
T5	1511	5	0	0
T6	2754	0	0	0
T7	1603	0	0	0
T23	2934	0	0	0
T24	1634	0	0	0
T25	912	0	0	0
T26	868	0	0	0
T27	2229	0	0	0
T28	1303	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	140	0	0
T4	9385	0	0	0
T5	1511	5	0	0
T6	2754	0	0	0
T7	1603	0	0	0
T23	2934	0	0	0
T24	1634	0	0	0
T25	912	0	0	0
T26	868	0	0	0
T27	2229	0	0	0
T28	1303	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39811950	138	0	0
StatusRise_A	39811950	138	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	138	0	0
T4	9385	0	0	0
T5	1511	4	0	0
T6	2754	0	0	0
T7	1603	0	0	0
T23	2934	0	0	0
T24	1634	0	0	0
T25	912	0	0	0
T26	868	0	0	0
T27	2229	0	0	0
T28	1303	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	138	0	0
T4	9385	0	0	0
T5	1511	4	0	0
T6	2754	0	0	0
T7	1603	0	0	0
T23	2934	0	0	0
T24	1634	0	0	0
T25	912	0	0	0
T26	868	0	0	0
T27	2229	0	0	0
T28	1303	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39811950	139	0	0
StatusRise_A	39811950	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	139	0	0
T4	9385	0	0	0
T5	1511	4	0	0
T6	2754	0	0	0
T7	1603	0	0	0
T23	2934	0	0	0
T24	1634	0	0	0
T25	912	0	0	0
T26	868	0	0	0
T27	2229	0	0	0
T28	1303	0	0	0
T43	0	5	0	0
T44	0	1	0	0
T45	0	1	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39811950	139	0	0
T4	9385	0	0	0
T5	1511	4	0	0
T6	2754	0	0	0
T7	1603	0	0	0
T23	2934	0	0	0
T24	1634	0	0	0
T25	912	0	0	0
T26	868	0	0	0
T27	2229	0	0	0
T28	1303	0	0	0
T43	0	5	0	0
T44	0	1	0	0
T45	0	1	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0