Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	979800636	36050	0	0
CgEnOn_A	979800636	26266	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	979800636	36050	0	0
T2	0	5	0	0
T4	150620	9	0	0
T5	14518	40	0	0
T6	35640	3	0	0
T7	17852	3	0	0
T13	0	5	0	0
T16	0	7	0	0
T23	32460	3	0	0
T24	35338	3	0	0
T25	197048	3	0	0
T26	37348	27	0	0
T27	24150	6	0	0
T28	21478	3	0	0
T43	0	37	0	0
T44	0	5	0	0
T154	0	30	0	0
T155	0	20	0	0
T156	0	15	0	0
T157	0	5	0	0
T159	0	10	0	0
T160	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	979800636	26266	0	0
T2	0	51	0	0
T4	150620	0	0	0
T5	14518	37	0	0
T6	35640	0	0	0
T7	17852	0	0	0
T10	0	86	0	0
T13	0	4	0	0
T16	0	7	0	0
T17	0	44	0	0
T18	0	42	0	0
T19	0	4	0	0
T23	32460	0	0	0
T24	35338	0	0	0
T25	197048	0	0	0
T26	37348	24	0	0
T27	24150	3	0	0
T28	21478	0	0	0
T32	0	21	0	0
T43	0	58	0	0
T44	0	5	0	0
T154	0	30	0	0
T155	0	20	0	0
T156	0	15	0	0
T157	0	5	0	0
T159	0	10	0	0
T160	0	10	0	0
T161	0	1	0	0
T162	0	18	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	41027343	153	0	0
CgEnOn_A	41027343	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027343	153	0	0
T4	5101	0	0	0
T5	629	4	0	0
T6	1802	0	0	0
T7	755	0	0	0
T13	0	1	0	0
T23	1539	0	0	0
T24	1577	0	0	0
T25	8708	0	0	0
T26	1622	0	0	0
T27	1041	0	0	0
T28	916	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027343	153	0	0
T4	5101	0	0	0
T5	629	4	0	0
T6	1802	0	0	0
T7	755	0	0	0
T13	0	1	0	0
T23	1539	0	0	0
T24	1577	0	0	0
T25	8708	0	0	0
T26	1622	0	0	0
T27	1041	0	0	0
T28	916	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20513269	153	0	0
CgEnOn_A	20513269	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513269	153	0	0
T4	2550	0	0	0
T5	314	4	0	0
T6	899	0	0	0
T7	377	0	0	0
T13	0	1	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	0	0	0
T26	811	0	0	0
T27	520	0	0	0
T28	458	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513269	153	0	0
T4	2550	0	0	0
T5	314	4	0	0
T6	899	0	0	0
T7	377	0	0	0
T13	0	1	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	0	0	0
T26	811	0	0	0
T27	520	0	0	0
T28	458	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20513269	153	0	0
CgEnOn_A	20513269	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513269	153	0	0
T4	2550	0	0	0
T5	314	4	0	0
T6	899	0	0	0
T7	377	0	0	0
T13	0	1	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	0	0	0
T26	811	0	0	0
T27	520	0	0	0
T28	458	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513269	153	0	0
T4	2550	0	0	0
T5	314	4	0	0
T6	899	0	0	0
T7	377	0	0	0
T13	0	1	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	0	0	0
T26	811	0	0	0
T27	520	0	0	0
T28	458	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20513269	153	0	0
CgEnOn_A	20513269	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513269	153	0	0
T4	2550	0	0	0
T5	314	4	0	0
T6	899	0	0	0
T7	377	0	0	0
T13	0	1	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	0	0	0
T26	811	0	0	0
T27	520	0	0	0
T28	458	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513269	153	0	0
T4	2550	0	0	0
T5	314	4	0	0
T6	899	0	0	0
T7	377	0	0	0
T13	0	1	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	0	0	0
T26	811	0	0	0
T27	520	0	0	0
T28	458	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	83935292	153	0	0
CgEnOn_A	83935292	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935292	153	0	0
T4	14078	0	0	0
T5	1296	4	0	0
T6	3074	0	0	0
T7	1603	0	0	0
T13	0	1	0	0
T23	2844	0	0	0
T24	3138	0	0	0
T25	17536	0	0	0
T26	3337	0	0	0
T27	2161	0	0	0
T28	1926	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935292	141	0	0
T4	14078	0	0	0
T5	1296	4	0	0
T6	3074	0	0	0
T7	1603	0	0	0
T23	2844	0	0	0
T24	3138	0	0	0
T25	17536	0	0	0
T26	3337	0	0	0
T27	2161	0	0	0
T28	1926	0	0	0
T43	0	7	0	0
T44	0	1	0	0
T154	0	6	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93072025	151	0	0
CgEnOn_A	93072025	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	151	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	0	0	0
T28	2006	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T68	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	144	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	0	0	0
T28	2006	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93072025	151	0	0
CgEnOn_A	93072025	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	151	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	0	0	0
T28	2006	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T68	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	144	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	0	0	0
T28	2006	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	44695070	144	0	0
CgEnOn_A	44695070	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44695070	144	0	0
T4	7039	0	0	0
T5	650	4	0	0
T6	1537	0	0	0
T7	801	0	0	0
T10	0	1	0	0
T23	1422	0	0	0
T24	1569	0	0	0
T25	8768	0	0	0
T26	1668	0	0	0
T27	1080	0	0	0
T28	963	0	0	0
T43	0	5	0	0
T44	0	1	0	0
T45	0	1	0	0
T69	0	1	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	2	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44695070	142	0	0
T4	7039	0	0	0
T5	650	4	0	0
T6	1537	0	0	0
T7	801	0	0	0
T10	0	1	0	0
T23	1422	0	0	0
T24	1569	0	0	0
T25	8768	0	0	0
T26	1668	0	0	0
T27	1080	0	0	0
T28	963	0	0	0
T43	0	5	0	0
T44	0	1	0	0
T45	0	1	0	0
T69	0	1	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	2	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T43,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20513269	5738	0	0
CgEnOn_A	20513269	3312	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513269	5738	0	0
T4	2550	3	0	0
T5	314	5	0	0
T6	899	1	0	0
T7	377	1	0	0
T23	768	1	0	0
T24	789	1	0	0
T25	4354	1	0	0
T26	811	10	0	0
T27	520	1	0	0
T28	458	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513269	3312	0	0
T2	0	15	0	0
T4	2550	0	0	0
T5	314	4	0	0
T6	899	0	0	0
T7	377	0	0	0
T10	0	27	0	0
T17	0	13	0	0
T18	0	15	0	0
T19	0	1	0	0
T23	768	0	0	0
T24	789	0	0	0
T25	4354	0	0	0
T26	811	9	0	0
T27	520	0	0	0
T28	458	0	0	0
T32	0	7	0	0
T43	0	7	0	0
T162	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T43,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	41027343	5797	0	0
CgEnOn_A	41027343	3371	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027343	5797	0	0
T4	5101	3	0	0
T5	629	5	0	0
T6	1802	1	0	0
T7	755	1	0	0
T23	1539	1	0	0
T24	1577	1	0	0
T25	8708	1	0	0
T26	1622	8	0	0
T27	1041	1	0	0
T28	916	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41027343	3371	0	0
T2	0	16	0	0
T4	5101	0	0	0
T5	629	4	0	0
T6	1802	0	0	0
T7	755	0	0	0
T10	0	28	0	0
T17	0	15	0	0
T18	0	14	0	0
T19	0	1	0	0
T23	1539	0	0	0
T24	1577	0	0	0
T25	8708	0	0	0
T26	1622	7	0	0
T27	1041	0	0	0
T28	916	0	0	0
T32	0	7	0	0
T43	0	7	0	0
T162	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T43,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	83935292	5794	0	0
CgEnOn_A	83935292	3356	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935292	5794	0	0
T4	14078	3	0	0
T5	1296	5	0	0
T6	3074	1	0	0
T7	1603	1	0	0
T23	2844	1	0	0
T24	3138	1	0	0
T25	17536	1	0	0
T26	3337	9	0	0
T27	2161	1	0	0
T28	1926	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83935292	3356	0	0
T2	0	15	0	0
T4	14078	0	0	0
T5	1296	4	0	0
T6	3074	0	0	0
T7	1603	0	0	0
T10	0	29	0	0
T17	0	16	0	0
T18	0	13	0	0
T19	0	1	0	0
T23	2844	0	0	0
T24	3138	0	0	0
T25	17536	0	0	0
T26	3337	8	0	0
T27	2161	0	0	0
T28	1926	0	0	0
T32	0	7	0	0
T43	0	7	0	0
T162	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T43,T44
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	44695070	5761	0	0
CgEnOn_A	44695070	3323	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44695070	5761	0	0
T4	7039	3	0	0
T5	650	5	0	0
T6	1537	1	0	0
T7	801	1	0	0
T23	1422	1	0	0
T24	1569	1	0	0
T25	8768	1	0	0
T26	1668	9	0	0
T27	1080	1	0	0
T28	963	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44695070	3323	0	0
T2	0	13	0	0
T4	7039	0	0	0
T5	650	4	0	0
T6	1537	0	0	0
T7	801	0	0	0
T10	0	30	0	0
T17	0	16	0	0
T18	0	15	0	0
T19	0	1	0	0
T23	1422	0	0	0
T24	1569	0	0	0
T25	8768	0	0	0
T26	1668	8	0	0
T27	1080	0	0	0
T28	963	0	0	0
T32	0	7	0	0
T43	0	5	0	0
T162	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T27,T16,T2
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93072025	2966	0	0
CgEnOn_A	93072025	2959	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	2966	0	0
T2	0	5	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T10	0	2	0	0
T16	0	7	0	0
T19	0	1	0	0
T22	0	8	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	3	0	0
T28	2006	0	0	0
T43	0	2	0	0
T107	0	2	0	0
T108	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	2959	0	0
T2	0	5	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T10	0	2	0	0
T16	0	7	0	0
T19	0	1	0	0
T22	0	8	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	3	0	0
T28	2006	0	0	0
T43	0	2	0	0
T107	0	2	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T27,T16,T2
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93072025	2941	0	0
CgEnOn_A	93072025	2934	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	2941	0	0
T2	0	5	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T10	0	2	0	0
T16	0	11	0	0
T19	0	1	0	0
T22	0	8	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	2	0	0
T28	2006	0	0	0
T43	0	2	0	0
T52	0	4	0	0
T108	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	2934	0	0
T2	0	5	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T10	0	2	0	0
T16	0	11	0	0
T19	0	1	0	0
T22	0	8	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	2	0	0
T28	2006	0	0	0
T43	0	2	0	0
T52	0	4	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T27,T16,T2
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93072025	2885	0	0
CgEnOn_A	93072025	2878	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	2885	0	0
T2	0	7	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T10	0	2	0	0
T16	0	8	0	0
T19	0	1	0	0
T22	0	8	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	3	0	0
T28	2006	0	0	0
T43	0	2	0	0
T52	0	3	0	0
T108	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	2878	0	0
T2	0	7	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T10	0	2	0	0
T16	0	8	0	0
T19	0	1	0	0
T22	0	8	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	3	0	0
T28	2006	0	0	0
T43	0	2	0	0
T52	0	3	0	0
T108	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T27,T16,T2
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	93072025	2957	0	0
CgEnOn_A	93072025	2950	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	2957	0	0
T2	0	7	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T10	0	2	0	0
T16	0	8	0	0
T19	0	1	0	0
T22	0	8	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	4	0	0
T28	2006	0	0	0
T43	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93072025	2950	0	0
T2	0	7	0	0
T4	14664	0	0	0
T5	1352	5	0	0
T6	3203	0	0	0
T7	1671	0	0	0
T10	0	2	0	0
T16	0	8	0	0
T19	0	1	0	0
T22	0	8	0	0
T23	2963	0	0	0
T24	3269	0	0	0
T25	18268	0	0	0
T26	3475	0	0	0
T27	2251	4	0	0
T28	2006	0	0	0
T43	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0