Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	193047	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

421927

1

T5

59

T6

33

T7

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	182528	1			T5	64		T6	48		T25	64
values[0x0]	204888	1			T5	19		T6	19		T7	16
values[0x1]	227558	1			T5	29		T6	17		T7	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	134821	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

480153

1

T5

66

T6

44

T7

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2468	1			T1	12		T4	1		T33	30
valid_sources[0x01]	2180	1			T28	1		T1	6		T33	29
valid_sources[0x02]	2026	1			T1	11		T19	1		T33	31
valid_sources[0x03]	2990	1			T25	3		T1	8		T22	4
valid_sources[0x04]	1998	1			T1	15		T33	41		T11	17
valid_sources[0x05]	3080	1			T28	2		T1	11		T21	1
valid_sources[0x06]	2411	1			T28	2		T1	11		T20	1
valid_sources[0x07]	2675	1			T1	9		T33	30		T11	34
valid_sources[0x08]	2107	1			T1	9		T33	32		T11	27
valid_sources[0x09]	2683	1			T1	12		T4	3		T33	22
valid_sources[0x0a]	2328	1			T1	13		T22	3		T33	31
valid_sources[0x0b]	2161	1			T1	15		T4	1		T33	32
valid_sources[0x0c]	2241	1			T1	7		T33	26		T11	35
valid_sources[0x0d]	2244	1			T1	10		T21	2		T33	34
valid_sources[0x0e]	2181	1			T5	4		T27	1		T1	14
valid_sources[0x0f]	4397	1			T25	1		T28	2		T1	10
valid_sources[0x10]	2145	1			T25	1		T27	2		T1	13
valid_sources[0x11]	2175	1			T1	16		T19	1		T4	3
valid_sources[0x12]	2253	1			T1	12		T21	2		T33	33
valid_sources[0x13]	2394	1			T1	8		T33	37		T34	3
valid_sources[0x14]	2331	1			T1	12		T33	36		T34	11
valid_sources[0x15]	2527	1			T1	10		T4	1		T33	28
valid_sources[0x16]	1854	1			T25	4		T1	14		T21	1
valid_sources[0x17]	2370	1			T28	2		T1	6		T4	1
valid_sources[0x18]	2625	1			T28	2		T1	14		T33	29
valid_sources[0x19]	2212	1			T1	7		T4	2		T33	36
valid_sources[0x1a]	2132	1			T27	1		T1	11		T4	7
valid_sources[0x1b]	2320	1			T1	12		T19	1		T22	7
valid_sources[0x1c]	2146	1			T25	1		T1	9		T33	30
valid_sources[0x1d]	2421	1			T25	4		T1	9		T33	34
valid_sources[0x1e]	2420	1			T28	1		T1	13		T33	41
valid_sources[0x1f]	2756	1			T25	2		T28	1		T1	14
valid_sources[0x20]	2487	1			T5	3		T6	2		T1	20
valid_sources[0x21]	2028	1			T25	1		T1	10		T21	1
valid_sources[0x22]	2166	1			T6	28		T1	14		T4	1
valid_sources[0x23]	2391	1			T1	14		T33	30		T11	37
valid_sources[0x24]	2360	1			T1	13		T33	27		T11	28
valid_sources[0x25]	2146	1			T5	4		T25	1		T1	13
valid_sources[0x26]	2841	1			T28	5		T1	14		T33	29
valid_sources[0x27]	2130	1			T25	1		T1	10		T4	5
valid_sources[0x28]	2428	1			T25	1		T1	8		T33	29
valid_sources[0x29]	2124	1			T1	11		T4	1		T33	34
valid_sources[0x2a]	2653	1			T27	1		T1	18		T4	1
valid_sources[0x2b]	2205	1			T1	7		T4	4		T33	37
valid_sources[0x2c]	2326	1			T1	12		T4	1		T33	29
valid_sources[0x2d]	2115	1			T1	14		T4	2		T33	23
valid_sources[0x2e]	2315	1			T1	7		T33	36		T11	28
valid_sources[0x2f]	3228	1			T28	1		T1	9		T33	26
valid_sources[0x30]	2736	1			T25	1		T28	3		T1	9
valid_sources[0x31]	2111	1			T25	1		T1	15		T33	18
valid_sources[0x32]	2224	1			T1	14		T4	1		T33	35
valid_sources[0x33]	1863	1			T28	2		T1	7		T33	25
valid_sources[0x34]	2201	1			T6	5		T25	2		T1	9
valid_sources[0x35]	2845	1			T1	25		T21	3		T4	5
valid_sources[0x36]	2193	1			T1	14		T4	4		T33	35
valid_sources[0x37]	2264	1			T1	13		T21	1		T33	31
valid_sources[0x38]	2434	1			T1	13		T4	6		T33	39
valid_sources[0x39]	2065	1			T25	1		T1	7		T21	2
valid_sources[0x3a]	2271	1			T1	15		T33	32		T11	31
valid_sources[0x3b]	3128	1			T1	10		T21	1		T4	1
valid_sources[0x3c]	3073	1			T1	20		T33	29		T11	31
valid_sources[0x3d]	2431	1			T1	6		T19	1		T22	1
valid_sources[0x3e]	1926	1			T1	11		T4	3		T33	30
valid_sources[0x3f]	1975	1			T1	9		T33	29		T11	37
valid_sources[0x40]	2696	1			T6	12		T1	8		T22	10
valid_sources[0x41]	2154	1			T25	1		T28	1		T1	11
valid_sources[0x42]	1903	1			T1	14		T4	5		T33	25
valid_sources[0x43]	2472	1			T1	8		T19	1		T33	35
valid_sources[0x44]	2007	1			T1	15		T4	1		T33	35
valid_sources[0x45]	2434	1			T1	11		T4	1		T33	23
valid_sources[0x46]	2407	1			T1	12		T4	1		T33	29
valid_sources[0x47]	2528	1			T25	4		T1	11		T20	1
valid_sources[0x48]	2574	1			T25	1		T1	15		T33	39
valid_sources[0x49]	2240	1			T1	8		T33	27		T34	3
valid_sources[0x4a]	3458	1			T25	2		T1	15		T33	31
valid_sources[0x4b]	2414	1			T25	1		T1	6		T4	1
valid_sources[0x4c]	2399	1			T1	8		T4	1		T33	35
valid_sources[0x4d]	2086	1			T5	13		T1	12		T4	3
valid_sources[0x4e]	2167	1			T1	14		T19	1		T33	25
valid_sources[0x4f]	2536	1			T1	7		T33	28		T11	23
valid_sources[0x50]	2471	1			T27	1		T1	13		T4	3
valid_sources[0x51]	3006	1			T1	15		T21	2		T4	3
valid_sources[0x52]	2414	1			T6	3		T27	1		T1	8
valid_sources[0x53]	2143	1			T1	13		T18	7		T33	30
valid_sources[0x54]	2177	1			T28	1		T1	12		T19	1
valid_sources[0x55]	2269	1			T1	13		T33	18		T11	31
valid_sources[0x56]	2723	1			T1	9		T33	38		T11	17
valid_sources[0x57]	2262	1			T28	2		T1	13		T19	1
valid_sources[0x58]	2087	1			T1	11		T33	33		T11	42
valid_sources[0x59]	2596	1			T1	11		T4	1		T33	23
valid_sources[0x5a]	2045	1			T1	12		T21	1		T4	1
valid_sources[0x5b]	2125	1			T25	1		T1	11		T33	29
valid_sources[0x5c]	2316	1			T7	40		T25	1		T1	14
valid_sources[0x5d]	2446	1			T28	1		T1	18		T4	4
valid_sources[0x5e]	2511	1			T28	1		T1	12		T33	36
valid_sources[0x5f]	2137	1			T1	12		T18	3		T4	1
valid_sources[0x60]	2133	1			T1	13		T33	34		T11	30
valid_sources[0x61]	1845	1			T1	16		T4	2		T33	26
valid_sources[0x62]	2160	1			T28	1		T1	8		T33	29
valid_sources[0x63]	2370	1			T1	9		T4	1		T33	30
valid_sources[0x64]	2079	1			T1	5		T21	2		T22	4
valid_sources[0x65]	2052	1			T1	10		T19	2		T4	3
valid_sources[0x66]	1938	1			T1	9		T33	30		T11	27
valid_sources[0x67]	2403	1			T1	11		T33	19		T11	17
valid_sources[0x68]	2179	1			T25	1		T1	11		T4	3
valid_sources[0x69]	2336	1			T6	1		T25	1		T1	14
valid_sources[0x6a]	2090	1			T1	12		T4	1		T33	29
valid_sources[0x6b]	2263	1			T28	2		T1	12		T21	2
valid_sources[0x6c]	2199	1			T1	10		T32	52		T33	23
valid_sources[0x6d]	2249	1			T1	9		T22	1		T4	3
valid_sources[0x6e]	2357	1			T28	3		T1	11		T20	1
valid_sources[0x6f]	3012	1			T6	5		T27	1		T28	1
valid_sources[0x70]	1820	1			T1	10		T18	1		T19	2
valid_sources[0x71]	2491	1			T1	15		T33	35		T11	27
valid_sources[0x72]	2186	1			T28	2		T1	21		T4	1
valid_sources[0x73]	2570	1			T1	7		T18	2		T20	6
valid_sources[0x74]	2595	1			T25	1		T27	1		T28	2
valid_sources[0x75]	2110	1			T1	12		T33	30		T11	20
valid_sources[0x76]	2476	1			T1	18		T33	30		T11	40
valid_sources[0x77]	2026	1			T27	1		T1	23		T22	2
valid_sources[0x78]	2242	1			T28	1		T1	5		T4	2
valid_sources[0x79]	3260	1			T25	1		T27	1		T1	11
valid_sources[0x7a]	2169	1			T28	3		T1	7		T33	35
valid_sources[0x7b]	2276	1			T25	1		T1	8		T33	30
valid_sources[0x7c]	3060	1			T6	2		T28	4		T1	13
valid_sources[0x7d]	2701	1			T27	3		T1	11		T4	1
valid_sources[0x7e]	2127	1			T28	2		T1	12		T18	23
valid_sources[0x7f]	2663	1			T1	5		T4	5		T33	28
valid_sources[0x80]	2044	1			T25	1		T1	11		T20	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

120137

1

T5

44

T6

24

T25

27

values[0x0]

all_enables

biggest_size

162438

1

T5

9

T6

8

T7

7

values[0x1]

all_enables

biggest_size

139352

1

T5

6

T6

1

T7

7