Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T22
0	1	Covered	T1,T23,T33
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T22
1	0	Covered	T44,T45,T46
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	153605121	8066	0	0
GateOpen_A	153605121	14660	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153605121	8066	0	0
T1	656702	58	0	0
T2	435194	0	0	0
T4	345185	0	0	0
T11	0	29	0	0
T13	0	49	0	0
T18	5056	4	0	0
T19	5973	0	0	0
T20	8766	0	0	0
T21	8174	0	0	0
T22	9349	4	0	0
T23	15004	14	0	0
T24	74381	0	0	0
T33	0	46	0	0
T88	0	4	0	0
T104	0	4	0	0
T190	0	14	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153605121	14660	0	0
T1	656702	71	0	0
T2	435194	4	0	0
T5	6239	4	0	0
T6	32224	0	0	0
T7	11529	0	0	0
T18	5056	4	0	0
T20	0	4	0	0
T21	0	4	0	0
T22	0	4	0	0
T25	27301	4	0	0
T26	51756	4	0	0
T27	4064	0	0	0
T28	51302	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T22
0	1	Covered	T1,T23,T33
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T22
1	0	Covered	T44,T45,T46
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	16488091	1928	0	0
GateOpen_A	16488091	3575	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16488091	1928	0	0
T1	70921	13	0	0
T2	48346	0	0	0
T4	37058	0	0	0
T11	0	5	0	0
T13	0	9	0	0
T18	542	1	0	0
T19	711	0	0	0
T20	993	0	0	0
T21	895	0	0	0
T22	1026	1	0	0
T23	1656	3	0	0
T24	8257	0	0	0
T33	0	13	0	0
T88	0	1	0	0
T104	0	1	0	0
T190	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16488091	3575	0	0
T1	70921	17	0	0
T2	48346	1	0	0
T5	680	1	0	0
T6	3561	0	0	0
T7	1270	0	0	0
T18	542	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	3016	1	0	0
T26	8368	1	0	0
T27	442	0	0	0
T28	5683	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T22
0	1	Covered	T1,T23,T33
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T22
1	0	Covered	T44,T45,T46
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	32976617	2034	0	0
GateOpen_A	32976617	3679	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32976617	2034	0	0
T1	141847	14	0	0
T2	96691	0	0	0
T4	74116	0	0	0
T11	0	8	0	0
T13	0	14	0	0
T18	1083	1	0	0
T19	1424	0	0	0
T20	1988	0	0	0
T21	1790	0	0	0
T22	2051	1	0	0
T23	3312	4	0	0
T24	16512	0	0	0
T33	0	11	0	0
T88	0	1	0	0
T104	0	1	0	0
T190	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32976617	3679	0	0
T1	141847	17	0	0
T2	96691	1	0	0
T5	1360	1	0	0
T6	7121	0	0	0
T7	2540	0	0	0
T18	1083	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	6031	1	0	0
T26	16735	1	0	0
T27	882	0	0	0
T28	11365	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T22
0	1	Covered	T1,T23,T33
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T22
1	0	Covered	T44,T45,T46
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	67807685	2056	0	0
GateOpen_A	67807685	3707	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67807685	2056	0	0
T1	292111	14	0	0
T2	193435	0	0	0
T4	148325	0	0	0
T11	0	7	0	0
T13	0	14	0	0
T18	2287	1	0	0
T19	2559	0	0	0
T20	3857	0	0	0
T21	3659	0	0	0
T22	4181	1	0	0
T23	6690	3	0	0
T24	33074	0	0	0
T33	0	12	0	0
T88	0	1	0	0
T104	0	1	0	0
T190	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67807685	3707	0	0
T1	292111	17	0	0
T2	193435	1	0	0
T5	2799	1	0	0
T6	14361	0	0	0
T7	5146	0	0	0
T18	2287	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	12169	1	0	0
T26	17768	1	0	0
T27	1827	0	0	0
T28	22835	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T22
0	1	Covered	T1,T23,T33
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T22
1	0	Covered	T44,T45,T47
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	36332728	2048	0	0
GateOpen_A	36332728	3699	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36332728	2048	0	0
T1	151823	17	0	0
T2	96722	0	0	0
T4	85686	0	0	0
T11	0	9	0	0
T13	0	12	0	0
T18	1144	1	0	0
T19	1279	0	0	0
T20	1928	0	0	0
T21	1830	0	0	0
T22	2091	1	0	0
T23	3346	4	0	0
T24	16538	0	0	0
T33	0	10	0	0
T88	0	1	0	0
T104	0	1	0	0
T190	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36332728	3699	0	0
T1	151823	20	0	0
T2	96722	1	0	0
T5	1400	1	0	0
T6	7181	0	0	0
T7	2573	0	0	0
T18	1144	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	6085	1	0	0
T26	8885	1	0	0
T27	913	0	0	0
T28	11419	1	0	0