Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169977620	25430	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169977620	25430	0	0
T1	395360	352	0	0
T2	272025	203	0	0
T3	0	110	0	0
T4	64580	0	0	0
T11	0	255	0	0
T12	0	225	0	0
T13	0	550	0	0
T14	0	279	0	0
T15	0	739	0	0
T16	0	204	0	0
T17	0	379	0	0
T18	5835	0	0	0
T19	9190	0	0	0
T20	6630	0	0	0
T21	9715	0	0	0
T22	5220	0	0	0
T23	4180	0	0	0
T24	40450	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	33995524	3775	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	3775	0	0
T1	79072	57	0	0
T2	54405	32	0	0
T3	0	18	0	0
T4	12916	0	0	0
T11	0	33	0	0
T12	0	30	0	0
T13	0	78	0	0
T14	0	47	0	0
T15	0	108	0	0
T16	0	27	0	0
T17	0	61	0	0
T18	1167	0	0	0
T19	1838	0	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	33995524	3721	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	3721	0	0
T1	79072	56	0	0
T2	54405	31	0	0
T3	0	18	0	0
T4	12916	0	0	0
T11	0	31	0	0
T12	0	33	0	0
T13	0	72	0	0
T14	0	47	0	0
T15	0	93	0	0
T16	0	27	0	0
T17	0	59	0	0
T18	1167	0	0	0
T19	1838	0	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	33995524	5129	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	5129	0	0
T1	79072	70	0	0
T2	54405	43	0	0
T3	0	22	0	0
T4	12916	0	0	0
T11	0	53	0	0
T12	0	44	0	0
T13	0	111	0	0
T14	0	58	0	0
T15	0	148	0	0
T16	0	41	0	0
T17	0	77	0	0
T18	1167	0	0	0
T19	1838	0	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	33995524	5099	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	5099	0	0
T1	79072	72	0	0
T2	54405	41	0	0
T3	0	22	0	0
T4	12916	0	0	0
T11	0	53	0	0
T12	0	43	0	0
T13	0	113	0	0
T14	0	56	0	0
T15	0	150	0	0
T16	0	41	0	0
T17	0	77	0	0
T18	1167	0	0	0
T19	1838	0	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	33995524	7706	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	7706	0	0
T1	79072	97	0	0
T2	54405	56	0	0
T3	0	30	0	0
T4	12916	0	0	0
T11	0	85	0	0
T12	0	75	0	0
T13	0	176	0	0
T14	0	71	0	0
T15	0	240	0	0
T16	0	68	0	0
T17	0	105	0	0
T18	1167	0	0	0
T19	1838	0	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0