Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T24,T33

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	33995524	31334392	0	0
AllClkBypReqTrue_A	33995524	86547	0	0
IoClkBypReqFalse_A	33995524	31280478	0	2409
IoClkBypReqTrue_A	33995524	135845	0	0
LcClkBypAckFalse_A	33995524	31343202	0	0
LcClkBypAckTrue_A	33995524	77737	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	31334392	0	0
T1	79072	74396	0	0
T2	54405	54382	0	0
T5	2770	2581	0	0
T6	2393	2349	0	0
T7	1339	1296	0	0
T18	1167	1035	0	0
T25	3041	2986	0	0
T26	924	914	0	0
T27	1884	1705	0	0
T28	3092	3064	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	86547	0	0
T1	79072	188	0	0
T2	54405	0	0	0
T11	0	678	0	0
T18	1167	0	0	0
T19	1838	118	0	0
T20	1326	74	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T26	924	4	0	0
T27	1884	39	0	0
T28	3092	0	0	0
T32	0	236	0	0
T33	0	419	0	0
T101	0	135	0	0
T105	0	263	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	31280478	0	2409
T1	79072	74264	0	3
T2	54405	54380	0	3
T5	2770	2579	0	3
T6	2393	2347	0	3
T7	1339	1294	0	3
T18	1167	1033	0	3
T25	3041	2984	0	3
T26	924	877	0	3
T27	1884	1742	0	3
T28	3092	3062	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	135845	0	0
T1	79072	308	0	0
T2	54405	0	0	0
T11	0	1182	0	0
T18	1167	0	0	0
T19	1838	410	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T26	924	39	0	0
T27	1884	0	0	0
T28	3092	0	0	0
T32	0	210	0	0
T33	0	804	0	0
T86	0	39	0	0
T87	0	106	0	0
T101	0	303	0	0
T103	0	376	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	31343202	0	0
T1	79072	74388	0	0
T2	54405	54382	0	0
T5	2770	2581	0	0
T6	2393	2349	0	0
T7	1339	1296	0	0
T18	1167	1035	0	0
T25	3041	2986	0	0
T26	924	918	0	0
T27	1884	1744	0	0
T28	3092	3064	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	77737	0	0
T1	79072	196	0	0
T2	54405	0	0	0
T4	12916	0	0	0
T11	0	447	0	0
T18	1167	0	0	0
T19	1838	258	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0
T32	0	147	0	0
T33	0	556	0	0
T86	0	31	0	0
T87	0	63	0	0
T101	0	46	0	0
T103	0	148	0	0
T105	0	259	0	0