Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	302301520	8462	0	0
TransStop_A	302301520	4414	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302301520	8462	0	0
T1	1265172	48	0	0
T2	806000	0	0	0
T5	11660	26	0	0
T6	59840	23	0	0
T7	21440	0	0	0
T18	9532	4	0	0
T21	0	15	0	0
T22	0	4	0	0
T24	0	16	0	0
T25	50708	30	0	0
T26	74040	0	0	0
T27	7612	0	0	0
T28	95152	30	0	0
T33	0	103	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302301520	4414	0	0
T1	1265172	20	0	0
T2	806000	0	0	0
T5	11660	23	0	0
T6	59840	14	0	0
T7	21440	0	0	0
T11	0	18	0	0
T18	9532	4	0	0
T21	0	2	0	0
T22	0	4	0	0
T24	0	11	0	0
T25	50708	28	0	0
T26	74040	0	0	0
T27	7612	0	0	0
T28	95152	21	0	0
T33	0	38	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	75575380	2127	0	0
TransStop_A	75575380	1106	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75575380	2127	0	0
T1	316293	12	0	0
T2	201500	0	0	0
T5	2915	7	0	0
T6	14960	6	0	0
T7	5360	0	0	0
T18	2383	1	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	0	2	0	0
T25	12677	8	0	0
T26	18510	0	0	0
T27	1903	0	0	0
T28	23788	10	0	0
T33	0	28	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75575380	1106	0	0
T1	316293	4	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	4	0	0
T7	5360	0	0	0
T11	0	11	0	0
T18	2383	1	0	0
T22	0	1	0	0
T24	0	1	0	0
T25	12677	8	0	0
T26	18510	0	0	0
T27	1903	0	0	0
T28	23788	7	0	0
T33	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	75575380	2136	0	0
TransStop_A	75575380	1116	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75575380	2136	0	0
T1	316293	12	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	4	0	0
T7	5360	0	0	0
T18	2383	1	0	0
T21	0	4	0	0
T22	0	1	0	0
T24	0	6	0	0
T25	12677	9	0	0
T26	18510	0	0	0
T27	1903	0	0	0
T28	23788	6	0	0
T33	0	29	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75575380	1116	0	0
T1	316293	4	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	2	0	0
T7	5360	0	0	0
T18	2383	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T24	0	4	0	0
T25	12677	8	0	0
T26	18510	0	0	0
T27	1903	0	0	0
T28	23788	4	0	0
T33	0	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	75575380	2129	0	0
TransStop_A	75575380	1116	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75575380	2129	0	0
T1	316293	12	0	0
T2	201500	0	0	0
T5	2915	7	0	0
T6	14960	8	0	0
T7	5360	0	0	0
T18	2383	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T24	0	1	0	0
T25	12677	7	0	0
T26	18510	0	0	0
T27	1903	0	0	0
T28	23788	7	0	0
T33	0	23	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75575380	1116	0	0
T1	316293	6	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	4	0	0
T7	5360	0	0	0
T11	0	7	0	0
T18	2383	1	0	0
T22	0	1	0	0
T24	0	1	0	0
T25	12677	6	0	0
T26	18510	0	0	0
T27	1903	0	0	0
T28	23788	6	0	0
T33	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	75575380	2070	0	0
TransStop_A	75575380	1076	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75575380	2070	0	0
T1	316293	12	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	5	0	0
T7	5360	0	0	0
T18	2383	1	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	0	7	0	0
T25	12677	6	0	0
T26	18510	0	0	0
T27	1903	0	0	0
T28	23788	7	0	0
T33	0	23	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75575380	1076	0	0
T1	316293	6	0	0
T2	201500	0	0	0
T5	2915	5	0	0
T6	14960	4	0	0
T7	5360	0	0	0
T18	2383	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T24	0	5	0	0
T25	12677	6	0	0
T26	18510	0	0	0
T27	1903	0	0	0
T28	23788	4	0	0
T33	0	9	0	0