Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10CoveredT26,T27,T1 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT26,T27,T1
11CoveredT26,T27,T1 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT26,T27,T1
10CoveredT5,T6,T7
11CoveredT5,T6,T7
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 82245757 82243348 0 0
selKnown1 203421702 203419293 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 82245757 82243348 0 0
T1 354169 354166 0 0
T2 241727 241724 0 0
T5 3398 3395 0 0
T6 17800 17797 0 0
T7 6348 6345 0 0
T18 2707 2704 0 0
T25 15077 15074 0 0
T26 33968 33965 0 0
T27 2197 2194 0 0
T28 28410 28407 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 203421702 203419293 0 0
T1 876333 876330 0 0
T2 580302 580299 0 0
T5 8394 8391 0 0
T6 43083 43080 0 0
T7 15435 15432 0 0
T18 6858 6855 0 0
T25 36507 36504 0 0
T26 53304 53301 0 0
T27 5481 5478 0 0
T28 68505 68502 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 32976212 32975409 0 0
selKnown1 67807234 67806431 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 32976212 32975409 0 0
T1 141846 141845 0 0
T2 96691 96690 0 0
T5 1359 1358 0 0
T6 7120 7119 0 0
T7 2539 2538 0 0
T18 1083 1082 0 0
T25 6031 6030 0 0
T26 16735 16734 0 0
T27 882 881 0 0
T28 11364 11363 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 67807234 67806431 0 0
T1 292111 292110 0 0
T2 193434 193433 0 0
T5 2798 2797 0 0
T6 14361 14360 0 0
T7 5145 5144 0 0
T18 2286 2285 0 0
T25 12169 12168 0 0
T26 17768 17767 0 0
T27 1827 1826 0 0
T28 22835 22834 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10CoveredT26,T27,T1 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT26,T27,T1
11CoveredT26,T27,T1 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT26,T27,T1
10CoveredT5,T6,T7
11CoveredT5,T6,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 32781849 32781046 0 0
selKnown1 67807234 67806431 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 32781849 32781046 0 0
T1 141403 141402 0 0
T2 96691 96690 0 0
T5 1359 1358 0 0
T6 7120 7119 0 0
T7 2539 2538 0 0
T18 1083 1082 0 0
T25 6031 6030 0 0
T26 8865 8864 0 0
T27 874 873 0 0
T28 11364 11363 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 67807234 67806431 0 0
T1 292111 292110 0 0
T2 193434 193433 0 0
T5 2798 2797 0 0
T6 14361 14360 0 0
T7 5145 5144 0 0
T18 2286 2285 0 0
T25 12169 12168 0 0
T26 17768 17767 0 0
T27 1827 1826 0 0
T28 22835 22834 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT5,T6,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT5,T6,T7
11CoveredT5,T6,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 16487696 16486893 0 0
selKnown1 67807234 67806431 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 16487696 16486893 0 0
T1 70920 70919 0 0
T2 48345 48344 0 0
T5 680 679 0 0
T6 3560 3559 0 0
T7 1270 1269 0 0
T18 541 540 0 0
T25 3015 3014 0 0
T26 8368 8367 0 0
T27 441 440 0 0
T28 5682 5681 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 67807234 67806431 0 0
T1 292111 292110 0 0
T2 193434 193433 0 0
T5 2798 2797 0 0
T6 14361 14360 0 0
T7 5145 5144 0 0
T18 2286 2285 0 0
T25 12169 12168 0 0
T26 17768 17767 0 0
T27 1827 1826 0 0
T28 22835 22834 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%