Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	33995524	2375479	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	2375479	0	58
T1	79072	22190	0	0
T2	54405	13795	0	1
T3	0	6856	0	1
T4	12916	0	0	0
T11	0	35926	0	0
T12	0	25302	0	1
T13	0	62843	0	1
T14	0	15278	0	0
T15	0	81427	0	0
T16	0	24468	0	1
T18	1167	0	0	0
T19	1838	0	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0
T29	0	746	0	1
T30	0	0	0	1
T38	0	0	0	1
T133	0	0	0	1
T134	0	0	0	1