Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	34923179	440515	0	0
clk_enables_rd_A	34923179	9885	0	0
clk_hints_rd_A	34923179	9393	0	0
extclk_ctrl_rd_A	34923179	12924	0	0
extclk_ctrl_regwen_rd_A	34923179	7184	0	0
jitter_enable_rd_A	34923179	18458	0	0
jitter_regwen_rd_A	34923179	7522	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34923179	440515	0	0
T1	79072	2388	0	0
T2	54405	0	0	0
T4	12916	0	0	0
T11	0	9019	0	0
T18	1167	0	0	0
T19	1838	0	0	0
T20	1326	0	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0
T33	0	8612	0	0
T78	0	11849	0	0
T79	0	9649	0	0
T80	0	1593	0	0
T81	0	461	0	0
T82	0	2601	0	0
T83	0	8491	0	0
T84	0	7651	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34923179	9885	0	0
T35	21182	0	0	0
T36	162659	0	0	0
T39	899	0	0	0
T41	0	25	0	0
T78	0	534	0	0
T79	0	165	0	0
T82	0	219	0	0
T83	0	194	0	0
T88	1904	9	0	0
T101	1665	0	0	0
T102	2998	0	0	0
T103	1919	0	0	0
T104	1073	0	0	0
T105	2298	0	0	0
T106	1946	0	0	0
T156	0	3	0	0
T157	0	7	0	0
T158	0	1	0	0
T159	0	124	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34923179	9393	0	0
T40	1623	0	0	0
T41	0	30	0	0
T45	1435	0	0	0
T78	0	429	0	0
T79	0	167	0	0
T82	0	148	0	0
T83	0	174	0	0
T156	1898	5	0	0
T157	0	12	0	0
T158	0	3	0	0
T159	0	116	0	0
T160	0	1	0	0
T161	2082	0	0	0
T162	813181	0	0	0
T163	965	0	0	0
T164	1715	0	0	0
T165	1392	0	0	0
T166	859	0	0	0
T167	2583	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34923179	12924	0	0
T3	34582	0	0	0
T4	12916	0	0	0
T19	1838	25	0	0
T20	1326	21	0	0
T21	1943	0	0	0
T22	1044	0	0	0
T23	836	0	0	0
T24	8090	0	0	0
T32	1590	0	0	0
T33	184372	0	0	0
T34	0	145	0	0
T35	0	97	0	0
T92	0	12	0	0
T105	0	52	0	0
T107	0	70	0	0
T135	0	18	0	0
T161	0	40	0	0
T168	0	26	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34923179	7184	0	0
T11	297566	0	0	0
T34	40210	69	0	0
T35	0	19	0	0
T39	899	0	0	0
T78	0	487	0	0
T79	0	175	0	0
T82	0	123	0	0
T83	0	135	0	0
T85	694	0	0	0
T86	748	0	0	0
T87	1487	0	0	0
T88	1904	0	0	0
T92	0	13	0	0
T101	1665	0	0	0
T102	2998	0	0	0
T103	1919	0	0	0
T132	0	35	0	0
T159	0	34	0	0
T169	0	50	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34923179	18458	0	0
T35	21182	0	0	0
T36	162659	0	0	0
T39	899	0	0	0
T41	0	685	0	0
T78	0	591	0	0
T79	0	402	0	0
T82	0	583	0	0
T83	0	234	0	0
T88	1904	142	0	0
T101	1665	0	0	0
T102	2998	0	0	0
T103	1919	0	0	0
T104	1073	0	0	0
T105	2298	0	0	0
T106	1946	0	0	0
T156	0	126	0	0
T157	0	480	0	0
T158	0	229	0	0
T159	0	615	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34923179	7522	0	0
T37	233256	0	0	0
T78	462105	522	0	0
T79	0	196	0	0
T82	0	154	0	0
T83	0	137	0	0
T159	0	84	0	0
T170	0	110	0	0
T171	0	475	0	0
T172	0	206	0	0
T173	0	373	0	0
T174	0	233	0	0
T175	1723	0	0	0
T176	1716	0	0	0
T177	1239	0	0	0
T178	1547	0	0	0
T179	1154	0	0	0
T180	1360	0	0	0
T181	2184	0	0	0
T182	1306	0	0	0