Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	101986572	436	0	0
StatusRise_A	101986572	436	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101986572	436	0	0
T40	4869	0	0	0
T44	2385	13	0	0
T45	4305	3	0	0
T46	0	2	0	0
T47	0	6	0	0
T156	5694	0	0	0
T161	6246	0	0	0
T162	2439543	0	0	0
T163	2895	0	0	0
T164	5145	0	0	0
T165	4176	0	0	0
T166	2577	0	0	0
T182	0	2	0	0
T183	0	9	0	0
T184	0	7	0	0
T185	0	15	0	0
T186	0	5	0	0
T187	0	16	0	0
T188	0	11	0	0
T189	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101986572	436	0	0
T40	4869	0	0	0
T44	2385	13	0	0
T45	4305	3	0	0
T46	0	2	0	0
T47	0	6	0	0
T156	5694	0	0	0
T161	6246	0	0	0
T162	2439543	0	0	0
T163	2895	0	0	0
T164	5145	0	0	0
T165	4176	0	0	0
T166	2577	0	0	0
T182	0	2	0	0
T183	0	9	0	0
T184	0	7	0	0
T185	0	15	0	0
T186	0	5	0	0
T187	0	16	0	0
T188	0	11	0	0
T189	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	33995524	151	0	0
StatusRise_A	33995524	151	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	151	0	0
T40	1623	0	0	0
T44	795	4	0	0
T45	1435	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	1898	0	0	0
T161	2082	0	0	0
T162	813181	0	0	0
T163	965	0	0	0
T164	1715	0	0	0
T165	1392	0	0	0
T166	859	0	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	1	0	0
T187	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	151	0	0
T40	1623	0	0	0
T44	795	4	0	0
T45	1435	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	1898	0	0	0
T161	2082	0	0	0
T162	813181	0	0	0
T163	965	0	0	0
T164	1715	0	0	0
T165	1392	0	0	0
T166	859	0	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	1	0	0
T187	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	33995524	139	0	0
StatusRise_A	33995524	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	139	0	0
T40	1623	0	0	0
T44	795	5	0	0
T45	1435	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	1898	0	0	0
T161	2082	0	0	0
T162	813181	0	0	0
T163	965	0	0	0
T164	1715	0	0	0
T165	1392	0	0	0
T166	859	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	139	0	0
T40	1623	0	0	0
T44	795	5	0	0
T45	1435	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	1898	0	0	0
T161	2082	0	0	0
T162	813181	0	0	0
T163	965	0	0	0
T164	1715	0	0	0
T165	1392	0	0	0
T166	859	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	33995524	146	0	0
StatusRise_A	33995524	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	146	0	0
T40	1623	0	0	0
T44	795	4	0	0
T45	1435	1	0	0
T47	0	2	0	0
T156	1898	0	0	0
T161	2082	0	0	0
T162	813181	0	0	0
T163	965	0	0	0
T164	1715	0	0	0
T165	1392	0	0	0
T166	859	0	0	0
T183	0	4	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	2	0	0
T187	0	6	0	0
T188	0	6	0	0
T189	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33995524	146	0	0
T40	1623	0	0	0
T44	795	4	0	0
T45	1435	1	0	0
T47	0	2	0	0
T156	1898	0	0	0
T161	2082	0	0	0
T162	813181	0	0	0
T163	965	0	0	0
T164	1715	0	0	0
T165	1392	0	0	0
T166	859	0	0	0
T183	0	4	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	2	0	0
T187	0	6	0	0
T188	0	6	0	0
T189	0	3	0	0